Publications


Research and Development Tool Releases

  1. JADE heterogeneous multiprocessor system design, modeling, and simulation environment
  2. COSMIC heterogeneous multiprocessor benchmark suite
  3. MCSL realistic network-on-chip traffic patterns
  4. PowerSoC power delivery system design, modeling, and analysis platform
  5. CLAP optical crosstalk and loss modeling and analysis platform
  6. OTemp optical thermal effect modeling and analysis platform
  7. OEIL optical and electrical interface and link design, modeling, and analysis platform
  8. BOSIM electro-optical silicon photonic device design, modeling, and simulation platform

Books and Book Chapters

  1. Peng Yang, Zhehui Wang, Zhifei Wang, Xuanqi Chen, Luan HK Duong, Jiang Xu, “Silicon Photonics Enabled Rack-Scale Many-Core System”, Many-Core Computing: Hardware and Software, Institute of Engineering and Technology, 2019.
  2. Mahdi Nikdast, Gabriela Nicolescu, Sebastien Le Beux, Jiang Xu, Photonic Interconnects for Computer Systems, River Publishers 2017.
  3. Vincent Lau, Jiang Xu, “Algorithms, Architecture and System-on-Chip Design for Wireless Applications”, to be published by Cambridge University Press.
  4. Peng Yang, Xiaowen Wu, Yaoyao Ye, Jiang Xu, “Unified Inter- and Intra-Chip Optical Interconnect Networks”, Photonic Interconnects for Computer Systems, River Publishers, 2017.
  5. Jiang Xu, Huaxi Gu, Wei Zhang, Weichen Liu, “FONoC: A Fat Tree Based Optical Networks-on-Chip for Multiprocessor System-on-Chip”, Integrated Optical Interconnect Architectures for Embedded Systems, Springer, 2013.
  6. Santanu Dutta, Jens Rennert, Tiehan Lv, Jiang Xu, Shengqi Yang, Wayne Wolf, “MPSoC Architectures for Video”, Multiprocessor Systems-on-Chips, Morgan Kaufmann, 2004.

Tutorials

  1. Silicon Photonics for Computing Systems: Opportunities, Challenges, and Implementations
    Jiang Xu, Shigeru Nakamura; Asia and South Pacific Design Automation Conference (ASP-DAC), 2017
  2. Inter/Intra-Chip Optical Interconnection Network: Opportunities, Challenges, and Implementations
    Jiang Xu, Shigeru Nakamura; IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2016.
  3. Inter/Intra-Chip Optical Networks
    Jiang Xu; IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips), 2016.
  4. Optical Network-on-Chip: An Emerging Technology for Energy-Efficient Multi-Core Systems
    Jiang Xu, Ian O’Connor, John Kim; IFIP/IEEE International Conference on Very Large Scale Integration, 2011.

Referred Journal Publications

  1. Collaborative Power Management through Knowledge Sharing among Multiple Devices
    Zhongyuan Tian, Zhe Wang, Jiang Xu, et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 7, pp. 1203-1215, July 2019.
  2. CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors
    Zhehui Wang, Zhifei Wang, Jiang Xu, et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019.
  3. Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect
    Xuanqi Chen, Zhifei Wang, Yi-Shing Chang, Jiang Xu, et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019.
  4. A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers
    Zhifei Wang, Peng Yang, Yi-Shing Chang, Jiang Xu, et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019.
  5. Multi-Domain Inter/Intra-Chip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems
    Peng Yang, Zhehui Wang, Zhifei Wang, Jiang Xu, Yi-Shing Chang, et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019.
  6. Crosstalk Noise Reduction through Adaptive Power Control in Inter/Intra-Chip Optical Networks
    Luan H. K. Duong, Peng Yang, Zhifei Wang, Yi-Shing Chang, Jiang Xu, et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 1, pp. 43-56, January 2019.
  7. A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems
    Weichen Liu, Zhe Wang, Peng Yang, Jiang Xu, Bin Li, Ravi Iyer, Ramesh Illikkal; IEEE Transactions on Multi-Scale Computing Systems, vol. 4, no. 2, pp. 113-126, April 2018.
  8. High-Radix Non-blocking Integrated Optical Switching Fabric for Data Center
    Zhifei Wang, Jiang Xu, et al.; IEEE/OSA Journal of Lightwave Technology, vol. 35, no. 19, pp. 4268-4281, October 2017.
  9. Workload-Aware Adaptive Power Delivery System Management for Many-Core Processors
    Haoran Li, Jiang Xu, et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 10, pp. 2076-2086, November 2017.
  10. Energy-Efficient Power Delivery System Paradigms for Many-Core Processors
    Haoran Li, Xuan Wang, Jiang Xu, et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 3, pp. 449-462, March 2017.
  11. Alleviate Chip Pin Constraint for Multicore Processor By On/Off-Chip Power Delivery System Codesign
    Xuan Wang, Jiang Xu, et al.; ACM Journal on Emerging Technologies in Computing Systems, vol. 13, no. 2, March 2017.
  12. Low-Loss High-Radix Integrated Optical Switch Networks for Software-Defined Servers
    Zhifei Wang, Zhehui Wang, Jiang Xu, et al.; IEEE/OSA Journal of Lightwave Technology, vol. 34, no. 18, pp. 4364-4375, September 2016.
  13. An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC
    Zhe Wang, Xuan Wang, Jiang Xu, et al.; IEEE Transactions on Very Large Scale Integration Systems, vol. 24, no. 12, pp. 3373-3386, December 2016.
  14. A Holistic Modelling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects
    Zhehui Wang, Jiang Xu, et al.; IEEE Transactions on Very Large Scale Integration Systems, vol. 24, no. 7, pp. 2462-2474, July 2016. [PDF]
  15. Coherent and Incoherent Crosstalk Noise Analyses in Inter/Intra-chip Optical Interconnection Networks
    Luan H. K. Duong, Zhehui Wang, Mahdi Nikdast, Jiang Xu, et al.; IEEE Transactions on Very Large Scale Integration Systems, vol. 24, no. 7, pp. 2475-2487, July 2016. [PDF]
  16. Distributed Sensor Network on Chip for Performance Optimization of Soft Error Tolerant Multiprocessor System-on-Chip
    Weichen Liu, Wei Zhang, Xuan Wang, Jiang Xu; IEEE Transactions on Very Large Scale Integration Systems, vol.24, no.4, pp.1546-1559, April 2016.
  17. Improve Chip Pin Performance Using Optical Interconnects
    Zhehui Wang, Jiang Xu, et al.; IEEE Transactions on Very Large Scale Integration Systems, vol.24, no.4, pp.1574-1587, April 2016. [PDF]
  18. Crosstalk Noise in WDM-based Optical Networks-on-Chip: a Formal Study and Comparison
    Mahdi Nikdast, Jiang Xu, et al.; IEEE Transactions on Very Large Scale Integration Systems, vol.23, no.11, pp.2552-2565, November 2015. [PDF]
  19. An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators
    Xuan Wang, Jiang Xu, et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.34, no.9, pp.1401-1414, September 2015.
  20. An Inter/Intra-chip Optical Network for Manycore Processors
    Xiaowen Wu, Jiang Xu, et al.; IEEE Transactions on Very Large Scale Integration Systems, vol.23, no.4, pp.678-691, April 2015. [PDF]
  21. Actively Alleviate Power-Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC
    Xuan Wang, Jiang Xu, et al.; IEEE Transactions on Very Large Scale Integration Systems. vol. 23, no. 2, pp. 266-279, February 2015.
  22. System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip
    Yaoyao Ye, Zhehui Wang, Peng Yang, Jiang Xu, et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 11, pp. 1718-1731, November 2014. [PDF]
  23. SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor
    Xiaowen Wu, Jiang Xu, et al.; ACM Journal on Emerging Technologies in Computing Systems, vol. 10 no. 4, May 2014. [PDF]
  24. A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip
    Luan H.K. Duong, Mahdi Nikdast, Sébastien Le Beux, Jiang Xu, et al.; IEEE Design & Test of Computers, vol. 31, no. 5, pp. 55-65, October 2014. [PDF]
  25. On-Chip Sensor Networks for Soft-Error Tolerant Real-Time Multiprocessor Systems-on-Chip
    Weichen Liu, Xuan Wang, Jiang Xu, et al.; ACM Journal on Emerging Technologies in Computing Systems, vol. 10, no. 2, pp. 15:1-15:20, February 2014.
  26. Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint
    Mahdi Nikdast, Jiang Xu, et al.; IEEE Transactions on Very Large Scale Integration Systems, vol. 99, pp. 1-14, February 2014. [PDF]
  27. Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip
    Mahdi Nikdast, Jiang Xu, et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 3, pp. 437-450, March 2014. [PDF]
  28. Floorplan Optimization of Fat-Tree Based Networks-on-Chip for Chip Multiprocessors
    Zhehui Wang, Jiang Xu, et al.; IEEE Transactions on Computers, vol. 63, no. 6, pp. 1446-1459, June 2014. [PDF]
  29. Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip
    Yiyuan Xie, Mahdi Nikdast, Jiang Xu, et al.; IEEE Transactions on Very Large Scale Integration Systems, vol. 21, no. 10, pp. 1823-1836, October 2013. [PDF]
  30. UNION: A Unified Inter/Intra-Chip Optical Network for Chip Multiprocessors
    Xiaowen Wu, Yaoyao Ye, Jiang Xu, et al.; IEEE Transactions on Very Large Scale Integration Systems, vol. 99, pp. 1-14, June 2013. [PDF]
  31. 3D Mesh-based Optical Network-on-Chip for Multiprocessor System-on-Chip
    Yaoyao Ye, Jiang Xu, et al.; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 4, pp. 584-596, April 2013. [PDF]
  32. On-Chip Sensor Network for Efficient Management of Power Gating Induced Power/Ground Noise in Multiprocessor System-on-Chip
    Weichen Liu, Yu Wang, Xuan Wang, Jiang Xu, et al.; IEEE Transactions on Parallel and Distributed Systems, vol. 24, no. 4, pp. 767-777, April 2013. [PDF]
  33. Five-Port Optical Router Based on Microring Switches for Photonic Networks-on-Chip
    Ruiqiang Ji, Jiang Xu, Lin Yang; IEEE Photonics Technology Letters, vol. 25, no. 5, March, 2013. [PDF]
  34. System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip
    Yaoyao Ye, Jiang Xu, et al.; IEEE Transactions on Very Large Scale Integration Systems, vol. 21, no. 2, pp. 292-305, February 2013. [PDF]
  35. A Formal Study on Topology and Floorplan Characteristics of Mesh and Torus-based Optical Networks-on-Chip
    Kai Feng, Yaoyao Ye, Jiang Xu; Microprocessors and Microsystems, June 2012. [PDF]
  36. A Torus-based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip
    Yaoyao Ye, Jiang Xu, et al.; ACM Journal on Emerging Technologies in Computing Systems, vol. 8, no 1, February 2012. [PDF]
  37. Crosstalk Noise Analysis and Optimization in 5×5 Hitless Silicon Based Optical Router for Optical Networks-on-Chip (ONoC)
    Yiyuan Xie, Jiang Xu, et al.; IEEE/OSA Journal of Lightwave Technology, vol. 30, no. 1, January, 2012. [PDF]
  38. Power Gating Aware Task Scheduling in MPSoC
    Yu Wang, Jiang Xu, et al.; IEEE Transactions on Very Large Scale Integration Systems, vol. 19, no. 10, October 2011.
  39. Satisfiability Modulo Graph Theory for Task Mapping and Scheduling on Multiprocessor Systems
    Weichen Liu, Zonghua Gu, Jiang Xu, et al.; IEEE Transactions on Parallel and Distributed Systems, vol. 22, no. 8, August 2011.
  40. Elimination of Cross-talk in Silicon-on-Insulator Waveguide Crossings with Optimized Angle
    Yiyuan Xie, Jiang Xu, et al.; Optical Engineering, vol. 50, no. 6, June, 2011.
  41. Coroutine-based Synthesis of Efficient Embedded Software from SystemC Models
    Weichen Liu, Jiang Xu, et al.; IEEE Embedded Systems Letters, vol.3, no.1, March. 2011.
  42. Novel RD-optimized VBSME with Matching Highly Data Re-usable Hardware Architecture
    Xing Wen, Oscar Au, Jiang Xu, et al.; IEEE Transactions on Circuits and Systems for Video Technology, vol.21, no.2, pp.206-219, Feb. 2011.
  43. Design of Butterfly-Fat-Tree Optical Network-on-Chip
    Huaxi Gu, Shiqing Wang, Yintang Yang, Jiang Xu; Optical Engineering, vol 49, issue 9, 2010.
  44. Simultaneous OTDM Demultiplexing and Data Format Conversion Using a D Flip-Flop
    Yiyuan Xie, Jianguo Zhang, Jiang Xu; Microwave and Optical Technology Letters, vol. 52 no. 2, pp. 398-400, February  2010.
  45. A New Distributed Congestion Control Mechanism for Networks-on-Chip
    Huaxi Gu, Jiang Xu, et al.; Telecommunication Systems, January 2010.
  46. Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs
    Jiang Xu, Wayne Wolf, Wei Zhang; IEEE Micro, vol. 29 no. 3, pp. 20-30, 2009. [PDF]
  47. Efficient Software Synthesis for Dynamic Single Appearance Scheduling of Synchronous Dataflow Graphs
    Weichen Liu, Zonghua Gu, Jiang Xu; IEEE Embedded Systems Letters, vol. 1 no. 3, pp. 69-72, 2009.
  48. Efficient 2D Area Management and Online Task Placement on Runtime Reconfigurable FPGAs
    Zonghua Gu, Weichen Liu, Jiang Xu, et al.; Microprocessors and Microsystems, vol. 33, pp. 374-387, August 2009.
  49. Reducing Wavelength Conversion Range in Space/Wavelength Switches
    Bey-Chi Lin, Chin-Tau Lea, Danny Tsang, Jiang Xu; IEEE Photonics Technology Letters, September 2008.
  50. A Design Methodology for Application-Specific Networks-on-Chip
    Jiang Xu, Wayne Wolf, Joerg Henkel, Srimat Chakradhar; ACM Transactions on Embedded Computing Systems, July 2006. [PDF]
  51. A Methodology for Architectural Design of Multimedia Multiprocessor SoCs
    Tiehan Lv, I. Burak Ozer, Srimat Chakradhar, Jiang Xu, Wayne Wolf, Joerg Henkel; IEEE Design & Test of Computers, January 2005.
  52. Augmenting Platform-based Design with Synthesis Tools
    Yuan Xie, Jiang Xu, Wayne Wolf; Journal of Circuits, Systems, and Computers, April 2003.

Conference Publications

  1. Co-Manage Power Delivery and Consumption for Manycore Systems Using Reinforcement Learning
    Haoran Li, Zhongyuan Tian, Rafael Kioji Vivas Maeda, Xuanqi Chen, Jun Feng, Jiang Xu, IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Diego CA, USA, November 2018.
  2. Decentralized Collaborative Power Management through Multi-Device Knowledge Sharing
    Zhongyuan Tian, Haoran Li, Rafael Kioji Vivas Maeda, Jun Feng, Jiang Xu, IEEE International Conference on Computer Design (ICCD), Orlando Florida, USA, October 2018.
  3. RSON: an Inter/Intra-Chip Silicon Photonic Network for Rack-Scale Computing Systems
    Peng Yang, Zhengbin Pang, Zhifei Wang, Zhehui Wang, Min Xie, Xuanqi Chen, Luan H.K. Duong, Jiang Xu, Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden, Germany, March 2018.
  4. Multi-Device Collaborative Management Through Knowledge Sharing
    Zhongyuan Tian, Zhe Wang, Haoran Li, Peng Yang, Rafael Kioji Vivas Maeda, Jiang Xu, Asia and South Pacific Design Automation Conference (ASP-DAC), Korea, January 2018.
  5. A Comprehensive Electro-Optical Model for Silicon Photonic Switches
    Xuanqi Chen, Zhifei Wang, Yi-Shing Chang, Jiang Xu, et al., IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, July 2018 (IEEE TCVLSI Best Paper).
  6. Cross-layer Optimization for High-radix Integrated Optical Switches in Data Centers
    Zhifei Wang, Peng Yang, Yi-Shing Chang, Jiang Xu, et al., IEEE Optical Interconnects Conference, Santa Fe, USA, June 2018.
  7. MOCA: an Inter/Intra-Chip Optical Network for Memory
    Zhehui Wang, Zhengbin Pang, Peng Yang, Jiang Xu, et al., Design Automation Conference (DAC), Austin, USA, 2017.
  8. Adaptive Power Delivery System Management for Many-Core Processors with On/Off-Chip Voltage Regulators
    Haoran Li, Jiang Xu, et al.; Design, Automation and Test in Europe Conference and Exhibition (DATE), Lausanne, Switzerland, 2017.
  9. Modular Reinforcement Learning for Self-Adaptive Energy Efficiency Optimization in Multicore System
    Zhe Wang, Zhongyuan Tian, Jiang Xu, et al.; Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2017.
  10. Fast and Accurate Exploration of Multi-Level Caches Using Hierarchical Reuse Distance
    Rafael Kioji Vivas Maeda, Qiong Cai, Jiang Xu, et al.; IEEE Symposium on High Performance Computer Architecture (HPCA), Austin, USA, 2017.
  11. Comparisons of a Novel Optical Space Switch and AWGR
    Zhifei Wang, Peng Yang, Jiang Xu, et al.; Photonics in Switching, New Orleans, USA, 2017.
  12. Thermal-Sensitive Design and Power Optimization for a 3D Torus-Based Optical NoC
    Kang Yao, Yaoyao Ye, Sudeep Pasricha, Jiang Xu; IEEE/ACM International Conference on Computer Aided Design (ICCAD), Irvine, USA, 2017.
  13. Inter/Intra-Chip Optical Interconnection Network: Opportunities, Challenges, and Implementations
    Peng Yang, Shigeru Nakamura, Kenichiro Yashiki, Zhehui Wang, Luan H. K. Duong, Zhifei Wang, Xuanqi Chen, Yuichi Nakamura, Jiang Xu; IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Japan, 2016.
  14. JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models
    Rafael K. V. Maeda, Peng Yang, Xiaowen Wu, Zhe Wang, Jiang Xu, et al.; HiPEAC Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, Prague, January 2016.
  15. Coherent Crosstalk Noise Analyses in Ring-based Optical Interconnects
    Luan H. K. Duong, Mahdi Nikdast, Jiang Xu, et al.; Design, Automation and Test in Europe Conference and Exhibition (DATE), Grenoble, France, March 2015.
  16. Adaptively Tolerate Power-Gating-Induced Power/Ground Noise under Process Variations
    Zhe Wang, Xuan Wang, Jiang Xu, et al.; Design, Automation and Test in Europe Conference and Exhibition (DATE), Grenoble, France, March 2015.
  17. Alleviate Chip I/O Pin Constraints for Multicore Processors through Optical Interconnects
    Zhehui Wang, Jiang Xu, et al.; Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, January 2015.
  18. CLAP: a Crosstalk and Loss Analysis Platform for Optical Interconnects
    Mahdi Nikdast, Luan H. K. Duong, Jiang Xu, et al.; IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Italy, September 2014.
  19. A Systematic Network-on-Chip Traffic Modeling and Generation Methodology
    Zhe Wang, Weichen Liu, Jiang Xu, et al.; IEEE Asia Pacific Conference on Circuits & Systems, Okinawa, Japan, November 2014.
  20. A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-based MPSoCs
    Zhe Wang, Weichen Liu, Jiang Xu, et al.; IEEE Computer Society Annual Symposium on VLSI, Florida, July 2014. [PDF]
  21. Holistic Modeling and Comparison of Inter-Chip Optical and Electrical Interconnects
    Zhehui Wang, Jiang Xu, et al.; Design Automation Conference (DAC), June 2014 (Poster).
  22. On the Impact of Crosstalk Noise in Optical Networks-on-Chip
    Mahdi Nikdast, Jiang Xu; Design Automation Conference (DAC), June 2014. (PhD forum)
  23. Characterizing Power Delivery Systems with On/Off-Chip Voltage Regulators for Many-Core Processors
    Xuan Wang, Jiang Xu, et al.; Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden, Germany, March 2014.
  24. Active Power-Gating-Induced Power/Ground Noise Alleviation Using Parasitic Capacitance of On-Chip Memories
    Xuan Wang, Jiang Xu, et al.; Design, Automation and Test in Europe Conference and Exhibition (DATE), Grenoble, France, March 2013. [PDF]
  25. System-level Analysis of Mesh-based Hybrid Optical-Electronic Network-on-Chip
    Yaoyao Ye, Jiang Xu, et al.; IEEE International Symposium on Circuits and Systems (ISCAS), May 2013. [PDF]
  26. A Network-on-Chip Benchmark Suite Based on Real Applications
    Weichen Liu, Zhe Wang, Xiaowen Wu, Jiang Xu, et al.; Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW), February 2013.
  27. Holistic Comparison of Optical Routers for Chip Multiprocessors
    Yaoyao Ye, Xiaowen Wu, Jiang Xu, et al.; IEEE International Conference on Anti-Counterfeiting, Security and Identification, Taipei, Taiwan, 2012. (Invited) [PDF]
  28. A Novel Low-Waveguide-Crossing Floorplan for Fat Tree Based Optical Networks-on-Chip
    Zhehui Wang, Jiang Xu, et al.; IEEE Optical Interconnects Conference, Santa Fe, New Mexico, May 2012. [PDF]
  29. Thermal Analysis for 3D Optical Network-on-Chip Based on a Novel Low-Cost 6x6 Optical Router
    Yaoyao Ye, Jiang Xu, et al.; IEEE Optical Interconnects Conference, Santa Fe, New Mexico, May 2012. [PDF]
  30. A NoC Traffic Suite Based on Real Applications
    Weichen Liu, Jiang Xu, et al.; IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2011. [PDF]
  31. Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip
    Yaoyao Ye, Jiang Xu, et al.; IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2011. [PDF]
  32. A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC
    Weichen Liu, Jiang Xu, et al.; IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2011. [PDF]
  33. Sub-pixel Downsampling of Video with Matching Highly Data Re-use Hardware Architecture
    Xing Wen, Oscar C. Au, Jiang Xu, et al.; IEEE International Symposium on Circuits and Systems (ISCAS),  Rio de Janeiro, Brazil, May 2011.
  34. MCSL: A Realistic Traffic Benchmark Suite for Network-on-Chip Studies
    Weichen Liu, Jiang Xu, et al.; Design Automation Conference (DAC), June 2011 (Poster).
  35. A Low-Overhead Hardware-Software Collaborated Approach for Soft-Error Tolerance
    Weichen Liu, Jiang Xu, et al.; Design Automation Conference (DAC), June 2011  (Poster).
  36. A Case Study of On-Chip Sensor Networks for Soft-Error Tolerant Multiprocessor Systems-on-Chip
    Weichen Liu, Xuan Wang, Jiang Xu, et al.; AMD Technical Forum and Exhibition, Taipei, Taiwan, October 2010 (Invited Poster).
  37. A Formal Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip for Chip Multiprocessors
    Mahdi Nikdast, Jiang Xu, et al.; AMD Technical Forum and Exhibition, Taipei, Taiwan, October 2010 (Best Poster Award).
  38. Crosstalk Noise and Bit Error Rate Analysis for Optical Network-on-Chip
    Yiyuan Xie, Mahdi Nikdast, Jiang Xu, et al.; Design Automation Conference  (DAC, acceptance rate: 24%), 2010. [PDF]
  39. UNION: A Unified Inter/Intra-Chip Optical Network for Chip Multiprocessors
    Xiaowen Wu, Yaoyao Ye, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang, Jiang Xu; IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), June 2010. (Invited) [PDF]
  40. A Hierarchical Hybrid Optical-Electronic Network-on-Chip
    Kwai Hung Mo, Yaoyao Ye, Xiaowen Wu, Wei Zhang, Weichen Liu, Jiang Xu; IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2010. [PDF]
  41. A low Power and Standard-Compliant RDO Motion Estimation Hardware Architecture for VBSME
    Xing Wen, Oscar C. Au, Jiang Xu, et al.; International Conference on Green Circuits and Systems, 2010.
  42. A Highly Data Reusable and Standard-Compliant Motion Estimation Hardware Architecture
    Xing Wen, Oscar C. Au, Jiang Xu, et al.; IEEE International Conference on Multimedia and Expo (ICME), 2010.
  43. Performance Evaluation of On-Chip Sensor Network (SENoC) in MPSoC
    Yao Wang, Yu Wang, Jiang Xu, et al.; International Conference on Green Circuits and Systems, 2010.
  44. Simulation and Analysis of P/G Noise in TSV based 3D MPSoC
    Shuai Tao, Yu Wang, Jiang Xu, et al.; International Conference on Green Circuits and Systems, 2010.
  45. A Case Study of On-Chip Sensor Network in Multiprocessor System-on-Chip
    Yu Wang, Jiang Xu, et al.; International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2009. [PDF]
  46. An Efficient Technique for Analysis of Minimal Buffer Requirements of Synchronous Dataflow Graphs with Model Checking
    Weichen Liu, Zonghua Gu, Jiang Xu, et al.; International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), 2009 (Best Paper Candidate). [PDF]
  47. 3D Optical NoC for MPSoC
    Yaoyao Ye, Lian Duan, Jiang Xu, et al.; IEEE International 3D System Integration Conference (3DIC), 2009. [PDF]
  48. A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip
    Huaxi Gu, Kwai Hung Mo, Jiang Xu, et al.; IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2009 (Best Paper - Honorable Mention Award). [PDF]
  49. A Low-power Fat Tree-based Optical Network-on-Chip for Multiprocessor System-on-Chip
    Huaxi Gu, Jiang Xu, et al.; Design, Automation and Test in Europe Conference and Exhibition (DATE), 2009. [PDF]
  50. On-Line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise
    Yan Xu, Weichen Liu, Yu Wang, Jiang Xu, et al.; IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2009. [PDF]
  51. A Novel Multiple Description Video Coding based on H.264/AVC Video Coding Standard
    Xing Wen, Oscar C. Au, Jiang Xu, et al.; IEEE International Symposium on Circuits and Systems (ISCAS), 2009.
  52. Design of 3D Optical Network on Chip
    Huaxi Gu, Jiang Xu; International Symposium on Photonics and Optoelectronics (SOPO), 2009. [PDF]
  53. Design ASNoC for Low-Power SoCs
    Jiang Xu, Wei Zhang, Mo Kwai Hung, Zili Shao; International System-on-Chip Design Conference (ISOCC), 2008. (Invited)
  54. A Novel Optical Mesh Network-on-Chip for Gigascale Systems-on-Chip
    Huaxi Gu, Jiang Xu, et al.; IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2008. [PDF]
  55. Design of Sparse Mesh for Optical Network on Chip
    Huaxi Gu, Jiang Xu,et al.; IEEE Asia Pacific Optical Communications (APOC), 2008.
  56. ODOR: a Microresonator-based High-performance Low-cost Router for Optical Networks-on-Chip
    Huaxi Gu, Jiang Xu, et al.; International Conference on Hardware-Software Codesign and System Synthesis (CODES), 2008. [PDF]
  57. A Methodology for Design, Modeling, and Analysis of Networks-on-Chip
    Jiang Xu, Wayne Wolf, Joerg Henkel, Srimat Chakradhar; IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, May 2005. [PDF]
  58. H.264 HDTV Decoder Using Application-Specific Networks-on-Chip
    Jiang Xu, Wayne Wolf, Srimat Chakradhar, Joerg Henkel; IEEE International Conference on Multimedia and Expo (ICME), Amsterdam, the Netherlands, July 2005. [PDF]
  59. A Case Study in Networks-on-Chip Design for Embedded Video
    Jiang Xu, Wayne Wolf, Joerg Henkel, Srimat Chakradhar, Tiehan Lv; Design, Automation and Test in Europe Conference and Exhibition (DATE), Paris, France, February 2004. [PDF]
  60. A Wave-Pipelined On-chip Interconnect Structure for Networks-on-Chip
    Jiang Xu, Wayne Wolf; IEEE Hot Interconnects (HOTI), Stanford, CA, August 2003. [PDF]
  61. Wave Pipelining for Application-Specific Networks-on-Chip
    Jiang Xu, Wayne Wolf; International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Grenoble, France, October 2002. [PDF]
  62. Platform-Based Design and the First Generation Dilemma
    Jiang Xu, Wayne Wolf; Electronic Design Processes Workshop (EDP), Monterey, CA, April 2002. [PDF]