Photonic Network and Computing Bibliography

The bibliography tries to cover inter/intra-chip optical network researches. We are constantly updating it. If there is any suggestion, please kindly drop us an email.

Since 2019

  1. Bohan Hu, Yinyi Liu, Zhenguo Liu, Wei Zhang, Jiang Xu*, “PCC: An End-to-End Compilation Framework for Neural Networks on Photonic-Electronic Accelerators,” in Proceedings of IEEE International Conference on Computer Design (ICCD), Milan, Italy, November 2024.
  2. Yuxiang Fu, Xuanqi Chen, Jiaxu Zhang, Shixi Chen, Jiang Xu*, “Towards Thermally Reliable Photonic Links for Multicore Processors,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, Tennessee, USA, July 2024.
  3. Chengeng Li, Fan Jiang, Shixi Chen, Xianbin Li, Jiaqi Liu, Wei Zhang, Jiang Xu*, “Towards Scalable GPU System with Silicon Photonic Chiplet,” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE), Valencia, Spain, March 2024.
  4. Xianbin Li, Jiaqi Liu, Yuying Zhang, Yinyi Liu, Jiaxu Zhang, Chengeng Li, Shixi Chen, Yuxiang Fu, Fengshi Tian, Wei Zhang, Jiang Xu*, “PhotonNTT: Energy-efficient Parallel Photonic Number Theoretic Transform Accelerator,” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE), Valencia, Spain, March 2024.
  5. Yuxiang Fu, Yinyi Liu, Jiaxu Zhang, Tianshu Hou, Ngai Wong, Jiang Xu*, “PINN-based Compact Model for On-chip Silicon Photonic Devices,” Design Automation Conference (DAC), San Francisco CA, USA, June 2024 (poster).
  6. Yinyi Liu, Bohan Hu, Zhenguo Liu, Peiyu Chen, Linfeng Du, Jiaqi Liu, Xianbin Li, Wei Zhang, Jiang Xu*, “FIONA: Photonic-Electronic Co-Simulation Framework and Transferable Prototyping for Photonic Accelerator” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, California, USA, October 2023.
  7. Chengeng Li (co-first author), Fan Jiang (co-first author), Shixi Chen, Xianbin Li, Yinyi Liu, Lin Chen, Xiao Li, Jiang Xu*, “RONet: Scaling GPU System with Silicon Photonic Chiplet” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, California, USA, October 2023.
  8. Min Tan, Jiang Xu, Siyang Liu, Junbo Feng, Hua Zhang, Chaonan Yao, Shixi Chen, Hangyu Guo, Gengshi Han, Zhanhao Wen, Bao Chen, Yu He, Xuqiang Zheng, Da Ming, Yaowen Tu, Qiang Fu, Nan Qi, Dan Li, Li Geng, Song Wen, Fenghe Yang, Huimin He, Fengman Liu, Haiyun Xue, Yuhang Wang, Ciyuan Qiu, Guangcan Mi, Yanbo Li, Tianhai Chang, Mingche Lai, Luo Zhang, Qinfen Hao, Mengyuan Qin, “Co-packaged optics (CPO): status, challenges, and solutions,” Frontiers of Optoelectronics, 2023.
  9. Chengeng Li, Fan Jiang, Shixi Chen, Jiaxu Zhang, Yinyi Liu, Yuxiang Fu, Jiang Xu*, “Accelerating Cache Coherence in Manycore Processor through Silicon Photonic Chiplet,” in Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Diego, California, USA, October 2022.
  10. Yinyi Liu, Jiaqi Liu, Yuxiang Fu, Shixi Chen, Jiaxu Zhang, Jiang Xu*, “PHANES: ReRAM-based Photonic Accelerators for Deep Neural Networks,” in Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, California, USA, July 2022.
  11. Yinyi Liu, Jiaxu Zhang, Jun Feng, Shixi Chen, Jiang Xu*, “Reduce Footprints of Multiport Interferometers by Cosine-Sine-Decomposition Unfolding,” in Proceedings of Optical Fiber Communication Conference and Exhibition (OFC), San Diego, California, USA, March 2022.
  12. Yinyi Liu, Jiaxu Zhang, Jun Feng, Shixi Chen, Jiang Xu*, “A Reliability Concern on Photonic Neural Networks,” Design, Automation and Test in Europe Conference and Exhibition (DATE), Antwerp, Belgium, March 2022.
  13. Zhifei Wang, Jun Feng, Jiang Xu*, Xuanqi Chen, Jiaxu Zhang, Shixi Chen, Yinyi Liu, “HERO: Pbit High-Radix Optical Switch based on Integrated Silicon Photonics for Data Center,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 4, pp. 908-921, April 2022.
  14. Xuanqi Chen, Yuxiang Fu, Jun Feng, Jiaxu Zhang, Shixi Chen, Jiang Xu*, “Improving the Thermal Reliability of Photonic Chiplets on Multicore Processors (Invited),” Elsevier Integration, the VLSI Journal, vol. 86, pp. 9-21, September 2022.
  15. Jun Feng, Jiaxu Zhang, Shixi Chen, Jiang Xu*, “Scalable Low-Power High-Performance Optical Network for Rack-Scale Computers”, Silicon Photonics for High-Performance Computing and Beyond, CRC 2022.
  16. Jun Feng, Shixi Chen, Jiaxu Zhang, Yuxiang Fu, Jiang Xu*, “Energy-Efficient High-Performance Photonic Backplane Network for Rack-Scale Computing Systems,” IEEE Computer Society Annual Symposium on VLSI, Pafos, Cyprus, July 2022.
  17. Jiaxu Zhang, Yinyi Liu, Jun Feng, Shixi Chen, Tongyu Wu, Xiaowen Dong, Jiang Xu*, "Energy-Efficient and Low-Cost Optical Neural Network," Optics and Photonics International Congress (OPIC), Yokohama, Japan, April 2022.
  18. Jiaxu Zhang, Yinyi Liu, Jun Feng, Shixi Chen, Xiaowen Dong, Wutong Yu, Jiang Xu*, “UONN: Energy-Efficient Optical Neural Network,” Asia Communications and Photonics Conference, 2021.
  19. Zhehui Wang, Zhifei Wang, Jiang Xu*, Jun Feng, Shixi Chen, Xuanqi Chen, Jiaxu Zhang, “Reduce Loss and Crosstalk in Integrated Silicon-Photonic Multistage Switching Fabrics through Multi-Chip Partition,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 1, pp. 101-114, January 2021.
  20. Xuanqi Chen, Jun Feng, Jiang Xu*, Jiaxu Zhang, Shixi Chen, “Simultaneously Tolerate Thermal and Process Variations through Indirect Feedback Tuning for Silicon Photonic Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 7, pp. 1409-1422, July 2021.
  21. Jun Feng, Shixi Chen, Jiaxu Zhang, Jiang Xu*, “Rejuvenate Post-Moore’s Law Computing with Photonics-Electronics Hybrid Systems,” in Proceedings of International Conference on IC Design and Technology, Dresden, Germany, September 2021.
  22. Zhehui Wang, Zhifei Wang, Jiang Xu*, Yi-Shing Chang, Jun Feng, Xuanqi Chen, Shixi Chen, Jiaxu Zhang, “CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 9, pp. 1820-1833, September 2020.
  23. Xuanqi Chen, Zhifei Wang, Yi-Shing Chang, Jiang Xu*, Jun Feng, Peng Yang, Zhehui Wang, Luan H.K. Duong, “Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 5, pp. 977-990, May 2020.
  24. Zhifei Wang, Peng Yang, Yi-Shing Chang, Jiang Xu*, Xuanqi Chen, Zhehui Wang, Jun Feng, "A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 3, pp. 640-653, March 2020.
  25. Peng Yang, Zhehui Wang, Zhifei Wang, Jiang Xu*, Yi-Shing Chang, Xuanqi Chen, Rafael Kioji Vivas Maeda, Feng Jun, "Multi-Domain Inter/Intra-Chip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 3, pp. 626-639, March 2020.
  26. Shixi Chen, Jiang Xu*, Xuanqi Chen, Zhifei Wang, Jun Feng, Jiaxu Zhang, Zhongyuan Tian, Xiao Li, “Efficient Optical Power Delivery System for Hybrid Electronic-Photonic Manycore Processors,” Design, Automation and Test in Europe Conference and Exhibition (DATE), Grenoble, France, March 2020.
  27. Peng Yang, Zhehui Wang, Zhifei Wang, Xuanqi Chen, Luan HK Duong, Jiang Xu*, “Silicon Photonics Enabled Rack-Scale Many-Core System”, Many-Core Computing: Hardware and Software, Institute of Engineering and Technology, 2019.
  28. Luan H. K. Duong, Peng Yang, Zhifei Wang, Yi-Shing Chang, Jiang Xu*, Zhehui Wang, Xuanqi Chen, "Crosstalk Noise Reduction through Adaptive Power Control in Inter/Intra-Chip Optical Networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 1, pp. 43-56, January 2019.
  29. Zhifei Wang, Jiang Xu*, Xuanqi Chen, Zhehui Wang, Zhehui Wang, Jun Feng, Jiaxu Zhang, Shixi Chen, “Systematic Exploration of High-Radix Integrated Silicon Photonic Switches for Datacenters,” IEEE/ACM International Conference on Computer Aided Design (ICCAD), Westminster CO, USA, November 2019.
  30. Jun Feng, Zhehui Wang, Zhifei Wang, Xuanqi Chen, Shixi Chen, Jiaxu Zhang, Jiang Xu*, “Scalable Low-Power High-Performance Rack-Scale Optical Network,” PHOTONICS in SC19, Denver, Colorado, November 2019.

...

2018

  1. Peng Yang, Zhengbin Pang, Zhifei Wang, Zhehui Wang, Min Xie, Xuanqi Chen, Luan H.K. Duong, Jiang Xu*,"RSON: an Inter/Intra-Chip Silicon Photonic Network for Rack-Scale Computing Systems," Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden, Germany, March 2018.
  2. Xuanqi Chen, Zhifei Wang, Yi-Shing Chang, Jiang Xu*, Peng Yang, Zhehui Wang, Luan H.K. Duong, "A Comprehensive Electro-Optical Model for Silicon Photonic Switches," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, July 2018 (IEEE TCVLSI Best Paper).
  3. Zhifei Wang, Peng Yang, Yi-Shing Chang, Jiang Xu*, Xuanqi Chen, Zhehui Wang, Luan H. K. Duong, "Cross-layer Optimization for High-radix Integrated Optical Switches in Data Centers," IEEE Optical Interconnects Conference, Santa Fe, USA, June 2018.
  4. D. Bertozzi, M. Gavanelli, and M. Nonato, “Wavelength-Routed Optical Networks-on-Chip: Design Methods and Tools to Bridge the Gap Between Logic Topologies and Physical Ones in 3D Architectures,” Great Lakes Symposium on VLSI, New York, NY, USA, 2018.
  5. M. Tala and D. Bertozzi, “Understanding the Design Space of Wavelength-Routed Optical NoC Topologies for Power-Performance Optimization,” IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018.
  6. S. Werner, P. Fotouhi, R. Proietti, X. Xiao, and S. J. B. Yoo, “Towards Energy-Efficient High-Throughput Photonic NoCs for 2.5D Integrated Systems: A Case for AWGRs,” IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2018.
  7. S. V. R. Chittamuru, I. G. Thakkar, V. Bhat, and S. Pasricha, “SOTERIA: Exploiting Process Variations to Enhance Hardware Security with Photonic NoC Architectures,” Design Automation Conference, New York, NY, USA, 2018.
  8. H. Jia, T. Zhou, Y. Zhao, Y. Xia, J. Dai, L. Zhang, J. Ding, X. Fu, and L. Yang, “Six-port optical switch for cluster-mesh photonic network-on-chip,” Nanophotonics, 2018.
  9. C. Zhang and J. E. Bowers, “Silicon photonic terabit/s network-on-chip for datacenter interconnection,” Optical Fiber Technology, 2018.
  10. B. G. Lee and N. Dupuis, “Silicon Photonic Switch Fabrics: Technology and Architecture,” Journal of Lightwave Technology, 2019.
  11. S. Vanwinkle and A. K. Kodi, “SHARP: Shared Heterogeneous Architecture with Reconfigurable Photonic Network-on-Chip,” J. Emerg. Technol. Comput. Syst., 2018.
  12. S. Pasricha, S. V. R. Chittamuru, I. G. Thakkar, and V. Bhat, “Securing Photonic NoC Architectures from Hardware Trojans,” IEEE/ACM International Symposium on Networks-on-Chip, Piscataway, NJ, USA, 2018.
  13. I. Cerutti, M. N. A. Acmad, R. Reyes, P. Castoldi, and N. Andriolli, “Scheduling in multi-wavelength ring-based optical networks-on-chip,” IEEE/OSA Journal of Optical Communications and Networking, 2018.
  14. H. Temuçin and K. M. İmre, “Scheduling computation and communication on a software-defined photonic Network-on-Chip architecture for high-performance real-time systems,” Journal of Systems Architecture, 2018.
  15. P. Grani and S. Bartolini, “Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPs,” J. Emerg. Technol. Comput. Syst., 2018.
  16. X. Xiao, Y. Zhang, R. Proietti, and S. J. B. Yoo, “Scalable AWGR-based All-to-All Optical Interconnects with 2.5D/3D Integrated Optical Interposers,” IEEE Photonics Society Summer Topical Meeting Series (SUM), 2018.
  17. M. C. Meyer, Y. Okuyama, and A. B. Abdallah, “SAFT-PHENIC: a thermal-aware microring fault-resilient photonic NoC,” The Journal of Supercomputing, 2018.
  18. J. Luo, V.-D. Pham, C. Killian, D. Chillet, I. O’Connor, O. Sentieys, and S. LE BEUX, “Run-Time management of energy-performance trade-off in Optical Network-on-Chip,” Design of Circuits and Integrated Systems, Lyon, France, 2018.
  19. M. R. Yahya, N. Wu, G. Yan, and Y. Yasir, “Review of Photonic and Hybrid On Chip Interconnects for MPSoCs in IoT Paradigm,” Saudi Computer Society National Computer Conference (NCC), 2018.
  20. E. Fusella and A. Cilardo, “Reducing Power Consumption of Lasers in Photonic NoCs Through Application-Specific Mapping,” J. Emerg. Technol. Comput. Syst., 2018.
  21. T. Zhou, H. Jia, J. Dai, S. Yang, L. Zhang, X. Fu, and L. Yang, “Rearrangeable-Nonblocking Five-Port Silicon Optical Switch for 2-D-Mesh Network on Chip,” IEEE Photonics Journal, 2018.
  22. B. Lin, S. Chen, Y. Huang, and C. Lea, “Power Minimization in Microring-Based Benes Networks,” IEEE Transactions on Communications, 2018.
  23. Y. Chuang, K. Chen, K. Lin, S. Fang, B. Li, and U. Schlichtmann, “PlanarONoC: Concurrent Placement and Routing Considering Crossing Minimization for Optical Networks-on-Chip*,” ACM/ESDA/IEEE Design Automation Conference (DAC), 2018.
  24. D. Liu, Z. Zhao, Z. Wang, Z. Ying, R. T. Chen, and D. Z. Pan, “OPERON: Optical-electrical Power-efficient Route Synthesis for On-chip Signals,” ACM/ESDA/IEEE Design Automation Conference (DAC), 2018.
  25. Z. Pan, S. Fu, L. Lu, D. Li, W. Chang, D. Liu, and M. Zhang, “On-chip cyclic-AWG-based 12x12 silicon wavelength routing switches with minimized port-to-port insertion loss fluctuation,” Photon. Res., PRJ, 2018.
  26. T. Zhou and H. Jia, “Method to optimize optical switch topology for photonic network-on-chip,” Optics Communications, 2018.
  27. P. Guo, W. Hou, L. Guo, Q. Yang, Y. Ge, and H. Liang, “Low Insertion Loss and Non-Blocking Microring-Based Optical Router for 3D Optical Network-on-Chip,” IEEE Photonics Journal, 2018.
  28. S. V. R. chittamuru, I. G. Thakkar, and S. Pasricha, “LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-Chip,” IEEE Transactions on Multi-Scale Computing Systems, 2018.
  29. N. Dupuis and B. G. Lee, “Impact of Topology on the Scalability of Mach–Zehnder-Based Multistage Silicon Photonic Switch Networks,” J. Lightwave Technol., JLT, 2018.
  30. S. V. R. Chittamuru, I. G. Thakkar, and S. Pasricha, “HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018.
  31. L. Yang, T. Zhou, H. Jia, S. Yang, J. Ding, X. Fu, and L. Zhang, “General architectures for on-chip optical space and mode switching,” Optica, 2018.
  32. H. Jia, T. Zhou, X. Fu, J. Ding, L. Zhang, and L. Yang, “Four-port mode-selective silicon optical router for on-chip optical interconnect,” Optics express, 2018.
  33. M. Tala, O. Schrape, M. Krstic, and D. Bertozzi, “Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip,” Conference on Design of Circuits and Integrated Systems (DCIS), 2018.
  34. Y. Ro, E. Lee, and J. H. Ahn, “Evaluating the Impact of Optical Interconnects on a Multi-Chip Machine-Learning Architecture,” Electronics, 2018.
  35. Y. Wang, M. A. Seyedi, R. Wu, J. Hulme, M. Fiorentino, R. G. Beausoleil, and K.-T. Cheng, “Energy-efficient channel alignment of dwdm silicon photonic transceivers,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018.
  36. M. Li, T.-M. Tseng, D. Bertozzi, M. Tala, and U. Schlichtmann, “CustomTopo: A Topology Generation Method for Application-specific Wavelength-routed Optical NoCs,” International Conference on Computer-Aided Design, New York, NY, USA, 2018.
  37. S. Pasricha, S. V. R. Chittamuru, and I. G. Thakkar, “Cross-Layer Thermal Reliability Management in Silicon Photonic Networks-on-Chip,” Great Lakes Symposium on VLSI, 2018.
  38. S. V. R. Chittamuru, D. Dang, S. Pasricha, and R. Mahapatra, “BiGNoC: Accelerating Big Data Computing with Application-Specific Photonic Network-on-Chip Architectures,” IEEE Transactions on Parallel and Distributed Systems, 2018.
  39. Q. Zhu, X. Jiang, Y. Yu, R. Cao, H. Zhang, D. Li, Y. Li, L. Zeng, X. Guo, Y. Zhang, and C. Qiu, “Automated Wavelength Alignment in a 4 × 4 Silicon Thermo-Optic Switch Based on Dual-Ring Resonators,” IEEE Photonics Journal, 2018.
  40. S. Khoroush, M. Reshadi, and A. Khademzadeh, “Application mapping in hybrid photonic networks-on-chip for reducing insertion loss,” J Supercomput, 2018.
  41. L. Zhu, K. Wang, D. Zhou, L. Liu, and H. Gu, “An Optimization Algorithm to Build Low Congestion Multi-Ring Topology for Optical Network-on-Chip,” IEICE Trans. Inf. & Syst., 2018.
  42. R. Cao, Y. Yang, H. Gu, and L. Huang, “A Thermal-Aware Power Allocation Method for Optical Network-on-Chip,” IEEE Access, 2018.
  43. Y. Zhang, N. Wu, G. Yan, and F. Ge, “A Reconfigurable Hybrid Electro-optical Network-on-Chip Architecture,” 2018.
  44. Y. Xu, J. Yang, and R. Melhem, “A Process-Variation-Tolerant Method for Nanophotonic On-Chip Network,” J. Emerg. Technol. Comput. Syst., 2018.
  45. M. Nonato, D. Bertozzi, M. Gavanelli, and A. Peano, “A network model for routing-fault-free wavelength selection in WRONoCs design,” Electronic Notes in Discrete Mathematics, 2018.
  46. A. Zhu, D. Chen, C. Xu, C. Hu, and A. Song, “A Fault Check Graph Approach for Photonic Router in Network on Chip,” IEEE 27th Asian Test Symposium (ATS), 2018.
  47. S. Pitris, M. Moralis-Pegios, T. Alexoudi, J. Lambrecht, X. Yin, J. Bauwelinck, Y. Ban, P. D. Heyn, M. Pantouvaki, J. V. Campenhout, R. Broeke, and N. Pleros, “A 40 Gb/s Chip-to-Chip Interconnect for 8-Socket Direct Connectivity Using Integrated Photonics,” IEEE Photonics Journal, 2018.

2017

  1. Zhifei Wang, Jiang Xu*, Peng Yang, Zhehui Wang, Luan Huu Kinh Duong, Xuanqi Chen, “High-Radix Non-blocking Integrated Optical Switching Fabric for Data Center,” IEEE/OSA Journal of Lightwave Technology, vol. 35, no. 19, pp. 4268-4281, October 2017.
  2. Zhehui Wang, Zhengbin Pang, Peng Yang, Jiang Xu*, Xuanqi Chen, Rafael Kioji Vivas Maeda, Zhifei Wang, Luan H. K. Duong, Haoran Li, Zhe Wang, “MOCA: an Inter/Intra-Chip Optical Network for Memory” Design Automation Conference (DAC), Austin TX, USA, 2017.
  3. Mahdi Nikdast, Gabriela Nicolescu, Sebastien Le Beux, Jiang Xu, Photonic Interconnects for Computer Systems, River Publishers 2017.
  4. Kang Yao, Yaoyao Ye, Sudeep Pasricha, Jiang Xu, “Thermal-Sensitive Design and Power Optimization for a 3D Torus-Based Optical NoC,” IEEE/ACM International Conference on Computer Aided Design (ICCAD), Irvine CA, USA, 2017.
  5. Peng Yang, Xiaowen Wu, Yaoyao Ye, Jiang Xu*, “Unified Inter- and Intra-Chip Optical Interconnect Networks”, Photonic Interconnects for Computer Systems, River Publishers, 2017.
  6. Zhifei Wang, Peng Yang, Jiang Xu*, Xuanqi Chen, Zhehui Wang, Luan H. K. Duong, “Comparisons of a Novel Optical Space Switch and AWGR” Photonics in Switching, New Orleans, LA, USA, 2017.
  7. Z. Wang, H. Gu, Y. Chen, Y. Yang, and K. Wang, “3D Network-on-Chip Design for Embedded Ubiquitous Computing Systems,” Journal of Systems Architecture - Embedded Systems Design, vol. 76, pp. 39–46, 2017.
  8. K. N. Dang, M. Meyer, Y. Okuyama, and A. B. Abdallah, “A Low-overhead Soft–hard Fault-tolerant Architecture, Design and Management Scheme for Reliable High-performance Many-core 3D-NoC Systems,” The Journal of Supercomputing, vol. 73, no. 6, pp. 2705–2729, 2017.
  9. T. Zhou, H. Jia, Y. Xia, and L. Yang, “A Method to Optimizing Optical Switch Topology for Photonic Network-on-Chip,” in 2017 IEEE 14th International Conference on Group IV Photonics (GFP), 2017, pp. 123–124.
  10. B. Asadi, M. Reshadi, and A. Khademzadeh, “A Routing Algorithm for Reducing Optical Loss in Photonic Networks-on-Chip,” Photon Netw Commun, vol. 34, no. 1, pp. 52–62, Aug. 2017.
  11. M. Scaffardi, M. N. Malik, E. Lazzeri, G. Meloni, F. Fresi, L. Potì, N. Andriolli, I. Cerutti, C. Klitis, and L. Meriggi, “A Silicon Microring Optical 2×2 Switch Exploiting Orbital Angular Momentum for Interconnection Networks up to 20 Gbaud,” Journal of Lightwave Technology, vol. 35, no. 15, pp. 3142–3148, 2017.
  12. M. Kennedy and A. K. Kodi, “CLAP-NET: Bandwidth Adaptive Optical Crossbar Architecture,” Journal of Parallel and Distributed Computing, vol. 100, pp. 130–139, 2017.
  13. R. Wu, Y. Wang, Z. Zhang, C. Zhang, C. L. Schow, J. E. Bowers and K.-T. Cheng, “Compact Modeling and Circuit-level Simulation of Silicon Nanophotonic Interconnects,” in 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pp. 602–605.
  14. Z. Zhang, R. Wu, Y. Wang, C. Zhang, E. J. Stanton, C. L. Schow, K. Cheng, and J. E. Bowers, “Compact Modeling for Silicon Photonic Heterogeneously Integrated Circuits,” Journal of Lightwave Technology, vol. 35, no. 14, pp. 2973–2980, 2017.
  15. G. Chandwani, R. Sen, and D. Datta, “Comprehensive Design Methodology for Control and Data Planes in Wavelength-routed Optical Networks,” Photonic Network Communications, vol. 33, no. 3, pp. 243–257, 2017.
  16. M. Ortín-Obón, M. Tala, L. Ramini, V. Viñals-Yufera, and D. Bertozzi, “Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 7, pp. 2081–2094, Jul. 2017.
  17. P. Grani, R. Proietti, V. Akella, and S. J. B. Yoo, “Design and Evaluation of AWGR-Based Photonic NoC Architectures for 2.5D Integrated High Performance Computing Systems,” in 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017, pp. 289–300.
  18. F. Lan, R. Wu, C. Zhang, Y. Pan, and K. T. Cheng, “DLPS: Dynamic Laser Power Scaling for Optical Network-on-Chip,” in Design Automation Conference (ASP-DAC), 2017 22nd Asia and South Pacific, 2017, pp. 726–731.
  19. J. L. Abellán, C. Chen, and A. Joshi, “Electro-photonic NoC Designs for Kilocore Systems,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 13, no. 2, p. 24, 2017.
  20. C. Killian, D. Chillet, S. Le Beux, V.-D. Pham, O. Sentieys, and I. O’Connor, “Energy and Performance Trade-off in Nanophotonic Interconnects Using Coding Techniques,” in Design Automation Conference (DAC), 2017 54th ACM/EDAC/IEEE, 2017, pp. 1–6.
  21. H. Li, S. L. Beux, M. J. Sepulveda, and I. O’connor, “Energy-Efficiency Comparison of Multi-Layer Deposited Nanophotonic Crossbar Interconnects,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 13, no. 4, p. 61, 2017.
  22. S. V. R. Chittamuru, I. G. Thakkar, and S. Pasricha, “Enhancing Process Variation Resilience in Photonic NoC Architectures,” Photonic Interconnects for Computing Systems: Understanding and Pushing Design Challenges, p. 385, 2017.
  23. S. Vahidifar and M. Reshadi, “Erratum to: Loss-aware Routing Algorithm for Photonic Networks on Chip,” J Super comput, vol. 73, no. 12, pp. 5515–5515, Dec. 2017.
  24. M. Meyer and A. B. Abdallah, “Fault-tolerant Photonic Network-on-Chip,” Photonic Interconnects for Computing Systems: Understanding and Pushing Design Challenges, p. 281, 2017.
  25. V. Krishnamoorthy, H. D. Thacker, O. Torudbakken, S. Müller, A. Srinivasan, P. J. Decker, H. Opheim, J. E. Cunningham, I. Shubin, X. Zheng, M. Dignum, K. Raj, E. Rongved, and R. Penumatcha, “From Chip to Cloud: Optical Interconnects in Engineered Systems,” J. Lightwave Technol., JLT, vol. 35, no. 15, pp. 3103–3115, Aug. 2017.
  26. V. K. Narayana, S. Sun, A. Mehrabian, V. J. Sorger, and T. El-Ghazawi, “HyPPI NoC: Bringing Hybrid Plasmonics to an Opto-electronic Network-on-Chip,” in Parallel Processing (ICPP), 2017 46th International Conference on, 2017, pp. 131–140.
  27. Nikdast, G. Nicolescu, J. Trajkovic, and O. Liboiron-Ladouceur, “Impact of Fabrication Non-Uniformity on Silicon Photonic Networks-on-Chip,” Photonic Interconnects for Computing Systems: Understanding and Pushing Design Challenges, p. 355, 2017.
  28. G. Thakkar, S. V. R. Chittamuru, and S. Pasricha, “Improving the Reliability and Energy-efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling,” in Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017, p. 4.
  29. D. Dang, S. V. R. Chittamuru, R. Mahapatra, and S. Pasricha, “Islands of Heaters: A Novel Thermal Management Framework for Photonic NoCs,” in Design Automation Conference (ASP-DAC), 2017 22nd Asia and South Pacific, 2017, pp. 306–311.
  30. M. Meyer, Y. Okuyama, and A. B. Abdallah, “Microring Fault-resilient Photonic Network-on-Chip for Reliable High-performance Many-core Systems,” The Journal of Supercomputing, vol. 73, no. 4, pp. 1567–1599, 2017.
  31. V. K. Narayana, S. Sun, A.-H. A. Badawy, V. J. Sorger, and T. El-Ghazawi, “MorphoNoC: Exploring the Design Space of a Configurable Hybrid NoC Using Nanophotonics,” Microprocessors and Microsystems, vol. 50, pp. 113–126, 2017.
  32. W. Li, B. Guo, X. Li, S. Yin, Y. Zhou, and S. Huang, “Nesting Ring Architecture of Multichip Optical Network on Chip for Many-core Processor Systems,” OE, OPEGAR, vol. 56, no. 3, p. 035106, Mar. 2017.
  33. F. G. de Magalhães, M. Nikdast, F. Hessel, O. Liboiron-Ladouceur, and G. Nicolescu, “Optical Interconnection Networks: The Need for Low-Latency Controllers,” Photonic Interconnects for Computing Systems: Understanding and Pushing Design Challenges, p. 73, 2017.
  34. Luo, A. Elantably, V. D. Pham, C. Killian, D. Chillet, S. Le Beux, O. Sentieys, and I. O'Connor, “Performance and Energy Aware Wavelength Allocation on Ring-based WDM 3D Optical NoC,” in 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pp. 1372–1377.
  35. Bakhtiar, M. Hosseinzadeh, and M. Reshadi, “Reliable Communications in Optical Network-on-Chip by Use of Fault Tolerance Approaches,” Optik - International Journal for Light and Electron Optics, vol. 137, pp. 186–194, May 2017.
  36. B. Ahmed, T. Yoshinaga, and A. B. Abdallah, “Scalable Photonic Networks-on-Chip Architecture Based on a Novel Wavelength-Shifting Mechanism,” IEEE Transactions on Emerging Topics in Computing, vol. PP, no. 99, pp. 1–1, 2017.
  37. E. Kakoulli, V. Soteriou, C. Koutsides, and K. Kalli, “Silica-Embedded Silicon Nanophotonic On-Chip Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 6, pp. 978–991, 2017.
  38. Cerutti, J. A. Corvera, S. M. Dumlao, R. Reyes, P. Castoldi, and N. Andriolli, “Simulation and FPGA-based Implementation of Iterative Parallel Schedulers for Optical Interconnection Networks,” Journal of Optical Communications and Networking, vol. 9, no. 4, pp. C76–C87, 2017.
  39. Y. Wang, K. Wang, D. Zhou, K. Wang, and H. Gu, “SOIN: Scalable Optical Interconnect Network for On-chip Parallel Memory Access,” in Asia Communications and Photonics Conference (2017), paper Su2A.56, 2017, p. Su2A.56.
  40. N. Li, T. Barwicz, W. Green, and D. Sadana, “Some Advances on Optical Interconnects,” in 2017 IEEE Photonics Conference (IPC), 2017, pp. 363–364.
  41. Wang, A. Nirmalathas, C. Lim, K. Alameh, and E. Skafidas, “Space-Time-Coded High-speed Reconfigurable Card-to-Card Free-space Optical Interconnects,” J. Opt. Commun. Netw., JOCN, vol. 9, no. 2, pp. A189–A197, Feb. 2017.
  42. S. V. R. Chittamuru, S. Desai, and S. Pasricha, “SWIFTNoC: A Reconfigurable Silicon-photonic Network with Multicast-enabled Channel Sharing for Multicore Architectures,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 13, no. 4, p. 58, 2017.
  43. Bai, H. Gu, Y. Chen, H. Zhang, X. Xu, and Y. Yang, “System-level Modeling and Performance Evaluation of Multistage Optical Network on Chips (MONoCs),” Photonic Network Communications, vol. 34, no. 1, pp. 25–33, 2017.
  44. T. Zhang, J. Klamkin, A. Joshi, and A. K. Coskun, “Thermal Management of Silicon Photonic NoCs in Many-core Systems,” Photonic Interconnects for Computing Systems: Understanding and Pushing Design Challenges, p. 227, 2017.
  45. Tinati, R. Karimi, S. Koohi, and S. Hessabi, “Topology Exploration of a Thermally Resilient Wavelength-based ONoC,” Journal of Parallel and Distributed Computing, vol. 100, pp. 140–156, Feb. 2017.
  46. M. Y. Teh, J. J. Wilke, K. Bergman, and S. Rumley, “Design Space Exploration of the Dragonfly Topology,” in High Performance Computing, 2017, pp. 57–74.
  47. Q. Cheng, M. Bahadori, S. Rumley, and K. Bergman, “Highly-scalable, Low-crosstalk Architecture for Ring-based Optical Space Switch Fabrics,” in IEEE Optical Interconnects Conference (OI), 2017, 2017, pp. 41–42.
  48. S. Rumley, M. Bahadori, R. Polster, S. D. Hammond, D. M. Calhoun, K. Wen, A. Rodrigues, and K. Bergman, “Optical Interconnects for Extreme Scale Computing Systems,” Parallel Computing, vol. 64, pp. 65–80, 2017.
  49. H. Guan, S. Rumley, K. Wen, D. Donofrio, J. Shalf, and K. Bergman, “Reconfigurable Silicon Photonic Interconnect for Many-Core Architecture,” in International Conference on High Performance Computing, 2017, pp. 89–97.
  50. Ortín-Obón, L. Ramini, V. Viñals-Yúfera, and D. Bertozzi, “A Tool for Synthesizing Power-efficient and Custom-tailored Wavelength-routed Optical Rings,” in 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 2017, pp. 300–305.
  51. L. Abellán, A. K. Coskun, A. Gu, W. Jin, A. Joshi, A. B. Kahng, J. Klamkin, C. Morales, J. Recchio, and V. Srinivas, “Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 5, pp. 801–814, 2017.
  52. H. Jia, Y. Xia, L. Zhang, J. Ding, X. Fu, and L. Yang, “Four-port Optical Switch for Fat-tree Photonic Network-on-Chip,” Journal of Lightwave Technology, vol. 35, no. 15, pp. 3237–3241, 2017.
  53. Dupuis, A. V. Rylyakov, C. L. Schow, D. M. Kuchta, C. W. Baks, J. S. Orcutt, D. M. Gill, W. M. J. Green, and B. G. Lee, “Nanosecond-Scale Mach–Zehnder-Based CMOS Photonic Switch Fabrics,” J. Lightwave Technol., JLT, vol. 35, no. 4, pp. 615–623, Feb. 2017.
  54. H. Jia, T. Zhou, L. Zhang, J. Ding, X. Fu, and L. Yang, “Optical Switch Compatible with Wavelength Division Multiplexing and Mode Division Multiplexing for Photonic Networks-on-Chip,” Optics express, vol. 25, no. 17, pp. 20698–20707, 2017.
  55. H. Jia, T. Zhou, L. Zhang, J. Ding, and L. Yang, “WDM-compatible 2×2 Optical Switch for Mode-division Multiplexing on a Silicon Chip,” in Group IV Photonics (GFP), 2017 IEEE 14th International Conference on, 2017, pp. 113–114.

2016

  1. Zhifei Wang, Zhehui Wang, Jiang Xu*, Peng Yang, Luan Huu Kinh Duong, Zhe Wang, Haoran Li, Rafael Kioji Vivas Maeda,"Low-Loss High-Radix Integrated Optical Switch Networks for Software-Defined Servers," IEEE/OSA Journal of Lightwave Technology, vol. 34, no. 18, pp. 4364-4375, September 2016.
  2. Zhehui Wang, Jiang Xu*, Peng Yang, Luan Huu Kinh Duong, Zhifei Wang, Xuan Wang, Zhe Wang, Haoran Li, Rafael Kioji Vivas Maeda, “A Holistic Modelling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects,” IEEE Transactions on Very Large Scale Integration Systems, vol. 24, no. 7, pp. 2462-2474, July 2016. [PDF]
  3. Luan H. K. Duong, Zhehui Wang, Mahdi Nikdast, Jiang Xu*, Peng Yang, Zhifei Wang, Zhe Wang, Rafael Kioji Vivas Maeda, Haoran Li, Xuan Wang, Sébastien Le Beux, Yvain Thonnart, “Coherent and Incoherent Crosstalk Noise Analyses in Inter/Intra-chip Optical Interconnection Networks,” IEEE Transactions on Very Large Scale Integration Systems, vol. 24, no. 7, pp. 2475-2487, July 2016. [PDF]
  4. Zhehui Wang, Jiang Xu*, Peng Yang, Xuan Wang, Zhe Wang, Luan H.K. Duong, Zhifei Wang, Rafael Kioji Vivas Maeda, Haoran Li, “Improve Chip Pin Performance Using Optical Interconnects,” IEEE Transactions on Very Large Scale Integration Systems, vol.24, no.4, pp.1574-1587, April 2016. [PDF]
  5. Peng Yang, Shigeru Nakamura, Kenichiro Yashiki, Zhehui Wang, Luan H. K. Duong, Zhifei Wang, Xuanqi Chen, Yuichi Nakamura, Jiang Xu*, “Inter/Intra-Chip Optical Interconnection Network: Opportunities, Challenges, and Implementations” IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Japan 2016.
  6. M. Bahadori, S. Rumley, H. Jayatilleka, K. Murray, N. A. F. Jaeger, L. Chrostowski, S. Shekhar, and K. Bergman, “Crosstalk Penalty in Microring-Based Silicon Photonic Interconnect Systems,” J. Lightwave Technol., JLT, vol. 34, no. 17, pp. 4043–4052, Sep. 2016.
  7. M. Bahadori, S. Rumley, D. Nikolova, and K. Bergman, “Comprehensive Design Space Exploration of Silicon Photonic Interconnects,” J. Lightwave Technol., JLT, vol. 34, no. 12, pp. 2975–2987, Jun. 2016.
  8. S. Rumley, M. Bahadori, K. Wen, D. Nikolova, and K. Bergman, “PhoenixSim: Crosslayer Design and Modeling of Silicon Photonic Interconnects,” in Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, New York, NY, USA, 2016, p. 7:1–7:6.
  9. P. Samadi, K. Wen, J. Xu, and K. Bergman, “Software-defined optical network for metro-scale geographically distributed data centers,” Opt. Express, OE, vol. 24, no. 11, pp. 12310–12320, May 2016.
  10. J. L. Abellán, C. Chen, and A. Joshi, “Electro-Photonic NoC Designs for Kilocore Systems,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 13, no. 2, p. 24, 2016.
  11. B. Asadi, M. Reshadi, and A. Khademzadeh, “A routing algorithm for reducing optical loss in photonic Networks-on-Chip,” Photonic Network Communications, pp. 1–11, 2016.
  12. S. Bahirat and S. Pasricha, “A Software Framework for Rapid Application-Specific Hybrid Photonic Network-on-Chip Synthesis,” Electronics, vol. 5, no. 2, p. 21, 2016.
  13. A. Ben Ahmed and A. Ben Abdallah, “An Energy-Efficient High-Throughput Mesh-Based Photonic On-Chip Interconnect for Many-Core Systems,” Photonics, vol. 3, no. 2, p. 15, Mar. 2016.
  14. R. Cao, K. Wang, H. Gu, B. Zhang, and X. Yu, “A crosstalk-aware wavelength assignment method for optical network-on-chip,” IEICE Electronic Express, vol. 13, no. 18, p. 20160821, 2016.
  15. I. Cerutti, A. M. Behredin, N. Andriolli, O. L. Ladouceur, and P. Castoldi, “Ring versus bus topology: A network performance comparison of photonic integrated NoC,” in Transparent Optical Networks (ICTON), 2016 18th International Conference on, 2016, pp. 1–4.
  16. I. Cerutti, J. A. Corvera, S. M. Dumlao, R. Reyes, P. Castoldi, and N. Andriolli, “Simulation and FPGA-based implementation of iterative parallel schedulers for optical interconnection networks,” Journal of Optical Communications and Networking, vol. 9, no. 4, pp. C76–C87, 2017.
  17. S. V. R. Chittamuru, I. G. Thakkar, and S. Pasricha, “PICO: mitigating heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs,” in Proceedings of the 53rd Annual Design Automation Conference, 2016, p. 39.
  18. S. V. R. Chittamuru, I. G. Thakkar, and S. Pasricha, “Process variation aware crosstalk mitigation for DWDM based photonic NoC architectures,” in Quality Electronic Design (ISQED), 2016 17th International Symposium on, 2016, pp. 57–62.
  19. J. A. Corvera, S. M. G. Dumlao, R. S. Reyes, P. Castoldi, N. Andriolli, and I. Cerutti, “Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks,” in Photonic Networks and Devices, 2016, p. NeM3B–4.
  20. F. G. de Magalhães, F. Hessel, O. Liboiron-Ladouceur, and G. Nicolescu, “Cluster-based architecture relying on Optical Integrated Networks with the provision of a low-latency arbiter,” in Integrated Circuits and Systems Design (SBCCI), 2016 29th Symposium on, 2016, pp. 1–6.
  21. F. G. de Magalhães, R. Priti, M. Nikdast, F. Hessel, O. Liboiron-Ladouceur, and G. Nicolescu, “Design and Modelling of a Low-Latency Centralized Controller for Optical Integrated Networks,” IEEE Communications Letters, vol. 20, no. 3, pp. 462–465, 2016.
  22. F. G. de Magalhães, Y. Xiong, F. Hessel, O. Liboiron-Ladouceur, and G. Nicolescu, “Co-design of an FPGA-based low-latency controller for MZI-based SiP switches,” in Photonics North (PN), 2016, 2016, pp. 1–1.
  23. Y. Demir and N. Hardavellas, “Energy-proportional photonic interconnects,” ACM Transactions on Architecture and Code Optimization (TACO), vol. 13, no. 4, p. 54, 2016.
  24. A. Descos, M. A. Seyedi, C. H. Chen, M. Fiorentino, F. Vincent, D. Penkler, B. Szelag, and R. G. Beausoleil, “Silicon photonics optical switch based on ring resonator,” in 2016 21st OptoElectronics and Communications Conference (OECC) held jointly with 2016 International Conference on Photonics in Switching (PS), 2016, pp. 1–3.
  25. A. Descos, M. A. Seyedi, C.-H. Chen, M. Fiorentino, R. G. Beausoleil, F. Vincent, D. Penkler, and B. Szelag, “Crosstalk analysis of ring-resonator based optical switches,” in IEEE Optical Interconnects Conference (OI), 2016, 2016, pp. 44–45.
  26. P. Dong, J. Lee, Y.-K. Chen, L. L. Buhl, S. Chandrasekhar, J. H. Sinsky, and K. Kim, “Four-Channel 100-Gb/s Per Channel Discrete Multitone Modulation Using Silicon Photonic Integrated Circuits,” J. Lightwave Technol., JLT, vol. 34, no. 1, pp. 79–84, Jan. 2016.
  27. P. Dong, “Silicon photonic integrated circuits for high-capacity optical communications,” in OptoElectronics and Communications Conference (OECC) held jointly with 2016 International Conference on Photonics in Switching (PS), 2016 21st, 2016, pp. 1–3.
  28. S. Faralli, N. Andriolli, F. Gambini, P. Pintus, G. Preve, M. Chiesa, R. Ortuño, O. Liboiron-Ladouceur, and I. Cerutti, “Bidirectional transmissions in a ring-based packaged optical NoC with 12 add-drop microrings,” in Photonics Conference (IPC), 2016 IEEE, 2016, pp. 621–622.
  29. S. Faralli, F. Gambini, P. Pintus, M. Scaffardi, O. Liboiron-Ladouceur, Y. Xiong, P. Castoldi, F. Di Pasquale, N. Andriolli, and I. Cerutti, “Bidirectional transmission in an optical network on chip with bus and ring topologies,” IEEE Photonics Journal, vol. 8, no. 2, pp. 1–7, 2016.
  30. S. Faralli, I. Cerutti, F. Gambini, P. Pintus, G. B. Preve, M. Chiesa, R. Ortuno, and N. Andriolli, “Characterization of a Packaged Network on Chip based on Multi-Microrings,” in ECOC 2016; 42nd European Conference on Optical Communication; Proceedings of, 2016, pp. 1–3.
  31. A. Funnell, J. Benjamin, H. Ballani, P. Costa, P. Watts, and B. C. Thomsen, “High port count hybrid wavelength switched TDMA (WS-TDMA) optical switch for data centers,” in Optical Fiber Communications Conference and Exhibition (OFC), 2016, 2016, pp. 1–3.
  32. P. Grani, R. Proietti, S. Cheung, and S. Yoo, “Flat-Topology High-Throughput Compute Node with AWGR-based Optical-Interconnects,” Journal of Lightwave Technology, vol. PP, no. 99, pp. 1–1, 2016.
  33. L. Huang, K. Wang, S. Qi, H. Gu, and Y. Yang, “Panzer: A 6 × 6 photonic router for optical network on chip,” IEICE Electronic Express, vol. 13, no. 21, p. 20160719, 2016.
  34. M. Imran, M. Collier, P. Landais, and K. Katrinis, “Performance evaluation of hybrid optical switch architecture for data center networks,” Optical Switching and Networking, vol. 21, pp. 1–15, Jul. 2016.
  35. H. Jia, Y. Zhao, L. Zhang, Q. Chen, J. Ding, X. Fu, and L. Yang, “5-port optical router based on Si microring optical switches for photonic networks-on-chip,” IEEE Photonics Technology Letters, vol. PP, no. 99, pp. 1–1, 2016.
  36. M. Kennedy and A. K. Kodi, “On-demand laser power allocation for on-chip optical interconnects,” in IEEE Optical Interconnects Conference (OI), 2016, 2016, pp. 68–69.
  37. H. Li, A. Fourmigue, S. Le Beux, I. O’Connor, and G. Nicolescu, “A thermal-Aware Laser Tuning Approach for Silicon Photonic Interconnects,” in The 2nd International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop), 2016.
  38. X. Li, H. Gu, K. Chen, L. Song, and Q. Hao, “STorus: A new topology for optical network-on-chip,” Optical Switching and Networking, vol. 22, pp. 77–85, 2016.
  39. D. Liang, M. Fiorentino, and R. G. Beausoleil, “VLSI Photonics for High-Performance Data Centers,” in Silicon Photonics III, L. Pavesi and D. J. Lockwood, Eds. Springer Berlin Heidelberg, 2016, pp. 489–516.
  40. F. Liu, H. Zhang, Y. Chen, Z. Huang, and H. Gu, “Dynamic Ring-Based Multicast with Wavelength Reuse for Optical Network on Chips,” in 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSOC 2016, Lyon, France, September 21-23, 2016, 2016, pp. 153–160.
  41. K. Liu, S. Sun, A. Majumdar, and V. J. Sorger, “Physical Scaling Laws of Nanophotonics,” in Frontiers in Optics, 2016, p. FTu3D–1.
  42. J. Luo, D. Chillet, C. Killian, S. L. Beux, I. O. ’Connor, and O. Sentieys, “Wavelength spacing optimization to reduce crosstalk in WDM 3D ONoC,” presented at the Conférence d’informatique en Parallélisme, Architecture et Système, 2016.
  43. J. Luo, D. Chillet, C. Killian, S. Le Beux, I. O’Connor, and O. Sentieys, “Crosstalk noise aware wavelength allocation in WDM 3D ONoC,” in Colloque National du GDR SoC-SiP, 2016.
  44. J. Luo, C. Killian, D. Chillet, S. Le Beux, I. O’Connor, O. Sentieys, and others, “POSTER: Wavelength Allocation for Efficient Communications on Optical Network-on-Chip,” in Conference on Design and Architectures for Signal and Image Processing, 2016, pp. 1656–1658.
  45. M. R. Madarbux, A. Van Laer, P. M. Watts, and T. M. Jones, “Energy Efficient And Low Latency Interconnection Network For Multicast Invalidates In Shared Memory Systems,” in Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2016, p. 1.
  46. M. Meyer, Y. Okuyama, and A. B. Abdallah, “A Power Estimation Method for Mesh-Based Photonic NoC Routing Algorithms,” in Computing and Networking (CANDAR), 2016 Fourth International Symposium on, 2016, pp. 451–453.
  47. M. Meyer, Y. Okuyama, and A. B. Abdallah, “Microring fault-resilient photonic network-on-chip for reliable high-performance many-core systems,” The Journal of Supercomputing, pp. 1–33, 2016.
  48. G. Miorandi, M. Tala, M. Balboni, L. Ramini, and D. Bertozzi, “Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems,” in Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, New York, NY, USA, 2016, p. 3:1–3:6.
  49. M. Nikdast, G. Nicolescu, J. Trajkovic, and O. Liboiron-Ladouceur, “An analytical study of process variations in silicon photonic integrated circuits,” in Photonics North (PN), 2016, 2016, pp. 1–2.
  50. M. Nikdast, G. Nicolescu, J. Trajkovic, and O. Liboiron-Ladouceur, “Enabling efficient tolerance analysis in silicon photonic integrated circuits,” in Progress in Electromagnetic Research Symposium (PIERS), 2016, pp. 783–783.
  51. M. Nikdast, G. Nicolescu, J. Trajkovic, and O. Liboiron-Ladouceur, “Modeling fabrication non-uniformity in chip-scale silicon photonic interconnects,” in Proceedings of the 2016 Conference on Design, Automation & Test in Europe, 2016, pp. 115–120.
  52. M. Nikdast, G. Nicolescu, J. Trajkovic, and O. Liboiron-Ladouceur, “Photonic integrated circuits: A study on process variations,” in Optical Fiber Communication Conference, 2016, p. W2A–22.
  53. M. Rafie, A. Khademzadeh, A. Reza, and M. Reshadi, “Performance evaluation of task migration in contiguous allocation for mesh interconnection topology,” The Journal of Supercomputing, vol. 72, no. 4, pp. 1660–1677, 2016.
  54. M. Scaffardi, M. N. Malik, E. Lazzeri, G. Meloni, F. Fresi, L. Poti, N. Andriolli, I. Cerutti, C. Klitis, L. Meriggi, and others, “A Silicon Microring Optical 2x2 Switch Exploiting Orbital Angular Momentum for Interconnection Networks up to 20Gbaud,” Journal of Lightwave Technology, 2016.
  55. O. Sentieys, J. Sepúlveda, S. Le Beux, J. Luo, C. Killian, D. Chillet, I. O’Connor, and H. Li, “Design Space Exploration of Optical Interfaces for Silicon Photonic Interconnects,” in 2th International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop), co-located with IEEE/ACM Design Automation and Test in Europe (DATE’16), 2016.
  56. M. A. Seyedi, A. Descos, C.-H. Chen, M. Fiorentino, D. Penkler, F. Vincent, B. Szelag, and R. G. Beausoleil, “Crosstalk analysis of ring resonator switches for all-optical routing,” Opt. Express, OE, vol. 24, no. 11, pp. 11668–11676, May 2016.
  57. H. Shabani, A. Roohi, A. Reza, M. Reshadi, N. Bagherzadeh, and R. F. DeMara, “Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks,” IEEE Transactions on Computers, vol. 65, no. 6, pp. 1789–1801, 2016.
  58. A. I. Sikder, A. K. Kodi, and A. Louri, “Reconfigurable Optical and Wireless (R-OWN) Network-on-Chip for High Performance Computing,” in Proceedings of the 3rd ACM International Conference on Nanoscale Computing and Communication, 2016, p. 25.
  59. M. Tala, M. Castellari, M. Balboni, and D. Bertozzi, “Populating and exploring the design space of wavelength-routed optical network-on-chip topologies by leveraging the add-drop filtering primitive,” in 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2016, pp. 1–8.
  60. M. Tala, M. O. Obòn, L. Ramini, M. Balboni, V. Vinals, and D. Bertozzi, “Contrasting Power Efficiency of Filter-vs. Ring-based Topologies for On-Chip Wavelength Routing with Layout Awareness,” in Asia Communications and Photonics Conference, 2016, p. ATh2E–5.
  61. I. G. Thakkar, S. V. R. Chittamuru, and S. Pasricha, “A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects,” in System Level Interconnect Prediction (SLIP), 2016 ACM/IEEE International Workshop on, 2016, pp. 1–8.
  62. I. G. Thakkar, S. V. R. Chittamuru, and S. Pasricha, “Mitigation of homodyne crosstalk noise in silicon photonic NoC architectures with tunable decoupling,” in Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016, p. 24.
  63. I. G. Thakkar, S. V. R. Chittamuru, and S. Pasricha, “Run-time laser power management in photonic NoCs with on-chip semiconductor optical amplifiers,” in Networks-on-Chip (NOCS), 2016 Tenth IEEE/ACM International Symposium on, 2016, pp. 1–4.
  64. B. Wang, C. Li, C.-H. Chen, K. Yu, M. Fiorentino, R. G. Beausoleil, and S. Palermo, “A Compact Verilog-A Model of Silicon Carrier-Injection Ring Modulators for Optical Interconnect Transceiver Circuit Design,” Journal of Lightwave Technology, vol. 34, no. 12, pp. 2996–3005, 2016.
  65. X. Wang, H. Gu, Y. Yang, K. Wang, and Q. Hao, “A Highly Scalable Optical Network-on-Chip With Small Network Diameter and Deadlock Freedom,” IEEE Trans. VLSI Syst., vol. 24, no. 12, pp. 3424–3436, 2016.
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2015

  1. M. Nikdast, J. Xu, L. Duong, X. Wu, X. Wang, Z. Wang, Z. Wang, P. Yang, Y. Ye, and Q. Hao, “Crosstalk noise in WDM-based optical networks-on-chip: a formal study and comparison,”IEEE Transactions Very Large Scale Integration (VLSI) Systems, vol.23, no.11, pp.2552-2565, November 2015. [PDF]
  2. Xiaowen Wu, Jiang Xu*, Yaoyao Ye, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Zhe Wang, “An Inter/Intra-chip Optical Network for Manycore Processors,” IEEE Transactions on Very Large Scale Integration Systems, vol.23, no.4, pp.678-691, April 2015. [PDF]
  3. Luan H. K. Duong, Mahdi Nikdast, Jiang Xu*, Zhehui Wang, Peng Yang, Yvain Thonnart, Sbastien Le Beux, Xiaowen Wu, Zhifei Wang, “Coherent Crosstalk Noise Analyses in Ring-based Optical Interconnects,” Design, Automation and Test in Europe Conference and Exhibition (DATE), Grenoble, France, March 2015.
  4. Zhehui Wang, Jiang Xu*, Peng Yang, Xuan Wang, Zhe Wang, Luan H.K. Duong, Zhifei Wang, Haoran Li, Rafael K.V. Maeda, Xiaowen Wu, Yaoyao Ye, Qinfen Hao, “Alleviate Chip I/O Pin Constraints for Multicore Processors through Optical Interconnects,” Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, January 2015.
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2014

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  46. R. Morris, E. Jolley, and A. Kodi, “Extending the performance and energy-efficiency of shared memory multicores with nanophotonic technology,” IEEE Transactions Parallel and Distributed Systems, vol. 25, no. 1, pp. 83-92, Jan 2014.
  47. R. Morris, A. Kodi, A. Louri, and R. Whaley, “Three-dimensional stacked nanophotonic network-on-chip architecture with minimal reconfiguration,” IEEE Transactions Computers, vol. 63, no. 1, pp. 243-255, Jan 2014.
  48. M. Notomi, K. Nozaki, A. Shinya, S. Matsuo, and E. Kuramochi, “Toward fJ/bit optical communication in a chip,” Optics Communications, vol. 314, pp. 3-17, 2014.
  49. M. Ortn-Obon, L. Ramini, H. Tatenguem Fankem, V. Vinals, and D. Bertozzi, “A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip,” in Proceedings 24th edition great lakes symposium VLSI. ACM, 2014, pp. 267- 272.
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  51. C. Peng, J. Lu, L. Zhou, C. Qin, L. Guo, and W. Dou, “Mathematical Model of a Three-Dimensional Optical Interconnection Network,” in 9th IEEE Networking, Architecture, and Storage (NAS) International Conference, 2014, pp. 24-32.
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2013

  1. Ruiqiang Ji, Jiang Xu*, Lin Yang, “Five-Port Optical Router Based on Microring Switches for Photonic Networks-on-Chip,” IEEE Photonics Technology Letters, vol. 25, no. 5, March, 2013. [PDF]
  2. Yaoyao Ye, Jiang Xu*, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu, “System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip,” IEEE Transactions on Very Large Scale Integration Systems, vol. 21, no. 2, pp. 292-305, February 2013. [PDF]
  3. Yaoyao Ye, Jiang Xu*, Baihan Huang, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu, Zhe Wang, “3D Mesh-based Optical Network-on-Chip for Multiprocessor System-on-Chip,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 4, pp. 584-596, April 2013. [PDF]
  4. Yiyuan Xie, Mahdi Nikdast, Jiang Xu*, Xiaowen Wu, Wei Zhang, Yaoyao Ye, Xuan Wang, Zhehui Wang, Weichen Liu, “Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip,” IEEE Transactions on Very Large Scale Integration Systems, vol. 21, no. 10, pp. 1823-1836, October 2013. [PDF]
  5. Yaoyao Ye, Jiang Xu*, Xiaowen Wu, et al., “System-level Analysis of Mesh-based Hybrid Optical-Electronic Network-on-Chip,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2013. [PDF]
  6. Chen, Z. Gu, H. Yang, Y. Bai, L. Li, H., “A Power Efficient and Compact Optical Interconnect for Network-on-Chip,” Computer Architecture Letters, vol.PP, no.99, pp.1, 1, 0
  7. Calo, G. Petruzzelli, V., “Wavelength Routers for Optical Networks-on-Chip Using Optimized Photonic Crystal Ring Resonators,” Photonics Journal, IEEE, vol.5, no.3, pp.7901011, 7901011, June 2013
  8. Ting Hu, Haifeng Shao, Longzhi Yang, Chao Xu, Mei Yang, Hui Yu, Xiaoqing Jiang, Jianyi Yang, “Four-Port Silicon Multi-Wavelength Optical Router for Photonic Networks-on-Chip,” Photonics Technology Letters, IEEE, vol.25, no.23, pp.2281, 2284, Dec.1, 2013
  9. Carpenter, J. Melhem, R., “Deterministic Multiplexing of NoC on Grid CMPs,” High-Performance Interconnects (HOTI), 2013 IEEE 21st Annual Symposium on, vol., no., pp.1, 8, 21-23 Aug. 2013
  10. Bartolini, S. Lusnig, L. Martinelli, E., “Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip Multiprocessors,” Digital System Design (DSD), 2013 Euromicro Conference on, vol., no., pp.56, 59, 4-6 Sept. 2013
  11. Parini, A. Bellanca, G. Annoni, A. Morichetti, F. Melloni, A. Strain, M.J. Sorel, M. Pareige, C. Gay, M. Bramerie, L. Thual, M., “Bit error rate performance evaluation of a Silicon-on-Insulator optical-network-on-chip router in a WDM configuration,” Optical Communication (ECOC 2013), 39th European Conference and Exhibition on, vol., no., pp.1, 3, 22-26 Sept. 2013
  12. Browning, M. Cheng Li, Gratz, P.V. Palermo, S., “LumiNOC: A low-latency, high-bandwidth per Watt, photonic Network-on-Chip,” System Level Interconnect Prediction (SLIP), 2013 ACM/IEEE International Workshop on, vol., no., pp.1, 4, 2-2 June 2013
  13. Ramini, Luca, Grani, Paolo, Bartolini, Sandro, Bertozzi, Davide, “Contrasting wavelength-routed optical NoC topologies for power-efficient 3d-stacked multicore processors using physical-layer analysis,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, vol., no., pp.1589, 1594, 18-22 March 2013
  14. Xianfang Tan, Mei Yang, Lei Zhang, Yingtao Jiang, Jianyi Yang, “Wavelength-routed optical networks-on-chip built with comb switches,” Photonics Conference (IPC), 2013 IEEE, vol., no., pp.46, 47, 8-12 Sept. 2013
  15. Hu, J. Li, L. Lin, H. Zou, Y. Gu, T. & Haney, M. “A fully-integrated flexible photonic platform for chip-to-chip optical interconnects,” Optical Interconnects Conference, 2013 IEEE, 2013, 128-129.
  16. Bamiedakis, N. Penty, R. & White, I. “Compact Multimode Polymer Waveguide Bends for Board-Level Optical Interconnects,” Lightwave Technology, Journal of, 2013, 31, 2370-2375.
  17. Maniotis, P. Fitsios, D. Kanellos, G. & Pleros, N. “Optical Buffering for Chip Multiprocessors: A 16GHz Optical Cache Memory Architecture Lightwave Technology,” Journal of, 2013, 31, 4175-4191.
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  20. C. Chen, A. Joshi, “Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture,” Selected Topics in Quantum Electronics, IEEE Journal of, vol.19, no.2, pp.338, 350, March-April 2013.
  21. Wang, K. Nirmalathas, A. Lim, C. Skafidas, E. & Alameh, K. “Performance of High-Speed Reconfigurable Free-Space Card-to-Card Optical Interconnects Under Air Turbulence,” Lightwave Technology, Journal of, 2013, 31, 1687-1693.
  22. Kinoshita, R. Moriya, K. Choki, K. & Ishigure, T. “Polymer Optical Waveguides With GI and W-Shaped Cores for High-Bandwidth-Density On-Board Interconnects,” Lightwave Technology, Journal of, 2013, 31, 4004-4015.
  23. Zhang, X. Hosseini, A. Lin, X. Subbaraman, H. & Chen, R. “Polymer-Based Hybrid-Integrated Photonic Devices for Silicon On-Chip Modulation and Board-Level Optical Interconnects,” Selected Topics in Quantum Electronics, IEEE Journal of, 2013, 19, 196-210.
  24. Bamiedakis, N. Hashim, A. Penty, R. & White, I. “A polymer waveguide-based 40 Gb/s optical bus backplane for board-level optical interconnects,” Transparent Optical Networks (ICTON), 2013 15th International Conference on, 2013, 1-5.
  25. Mu, J. Ragunathan, V. Zhang, L. Okamoto, S. Kimerling, L. & Michel, J. “Development of a chip-to-chip optical interconnect system,” Optical Interconnects Conference, 2013 IEEE, 2013, 116-117.
  26. Hatori, N. Shimizu, T. Okano, M. Ishizaka, M. Yamamoto, T. Urino, Y. Mori, M. Nakamura, T. & Arakawa, Y. “Low power consumption operation of light sources for inter-chip optical interconnects,” Indium Phosphide and Related Materials (IPRM), 2013 International Conference on, 2013, 1-2.
  27. De Dobbelaere, P. “Silicon photonics technology platform for embedded and integrated optical interconnect systems,” Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific, 2013, 644-647.
  28. Zeng, M.-Y. Chen, C.-T. Shen, P.-K. Liang, K. Chang, C.-C. Hsiao, H.-L. Lan, H.-C. Lee, Y.-C. Lin, Y.-S. & Wu, M.-L. “10-Gbit/s on-chip optical interconnect module using silicon-based 45 micro-reflectors terminated polymer waveguides,” Microoptics Conference (MOC), 2013 18th, 2013, 1-2.
  29. Datta, I. Datta, D. & Pratim Pande, P. “Design Methodology for Optical Interconnect Topologies in NoCs With BER and Transmit Power Constraints,” Journal of Lightwave Technology, IEEE, 2014, 32, 163-175.
  30. Laer, A. V. Jones, T. & Watts, P. M. “Full System Simulation of Optically Interconnected Chip Multiprocessors Using gem5,” Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2013, 2013.
  31. Li, H. Gu, H. Yang, Y. & Zhu, Z. “Impact of thermal effect on reliability in Optical Network-on-Chip,” Optik - International Journal for Light and Electron Optics, 2013.
  32. Sebastien Le Beux, Ian O’Connor, Gabriela Nicolescu, Guy Bois, Pierre Paulin, “Reduction methods for adapting optical network on chip topologies to 3D architectures,” Microprocessors and Microsystems (MICPRO), 2013, 37, 87-98.
  33. Randy Morris, Avinash Karanth Kodi and Ahmed Louri,“Evaluating the Scalability and Performance of 3D Stacked Reconfigurable Nanophotonic Interconnects,” IEEE/ACM System Level Interconnect Prediction, 2013.
  34. Li Zhou and Avinash Karanth Kodi, “PROBE: Prediction-based Optical Bandwidth Scaling for Energy-Efficient NoCs,” IEEE/ACM International Symposium on Networks-on-Chip (NoCs), 2013.

2012

  1. Yaoyao Ye, Jiang Xu*, Xiaowen Wu, Wei Zhang, Weichen Liu, Mahdi Nikdast, “A Torus-based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip,” ACM Journal on Emerging Technologies in Computing Systems, vol. 8, no 1, February 2012. [PDF]
  2. Yiyuan Xie, Jiang Xu*, Jianguo Zhang, Zhengmao Wu, Guangqiong Xia, “Crosstalk Noise Analysis and Optimization in 55 Hitless Silicon Based Optical Router for Optical Networks-on-Chip (ONoC),” IEEE/OSA Journal of Lightwave Technology, vol. 30, no. 1, January, 2012. [PDF]
  3. Zhehui Wang, Jiang Xu*, Xiaowen Wu, Yaoyao Ye, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang, Zhe Wang, “A Novel Low-Waveguide-Crossing Floorplan for Fat Tree Based Optical Networks-on-Chip,” IEEE Optical Interconnects Conference, Santa Fe, New Mexico, May 2012. [PDF]
  4. Yaoyao Ye, Jiang Xu*, Xiaowen Wu, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang, Zhehui Wang, Zhe Wang, “Thermal Analysis for 3D Optical Network-on-Chip Based on a Novel Low-Cost 6x6 Optical Router,” IEEE Optical Interconnects Conference, Santa Fe, New Mexico, May 2012. [PDF]
  5. Kai Feng, Yaoyao Ye, Jiang Xu*, “A Formal Study on Topology and Floorplan Characteristics of Mesh and Torus-based Optical Networks-on-Chip,” Microprocessors and Microsystems, June 2012.[PDF]
  6. Yaoyao Ye, Xiaowen Wu, Jiang Xu*, Wei Zhang, Mahdi Nikdast, Xuan Wang, “Holistic Comparison of Optical Routers for Chip Multiprocessors,” in Proceedings of IEEE International Conference on Anti-Counterfeiting, Security and Identification, Taipei, Taiwan, 2012.(Invited) [PDF]
  7. B.-C. Lin and C.-T. Lea, “Crosstalk Analysis for Microring Based Optical Interconnection Networks,” Journal of Lightwave Technology, vol. 30, no. 15, pp. 2415-2420, Aug. 1, 2012.
  8. Z. Li, M. Mohamed, X. Chen, E. Dudley, K. Meng, L. Shang, A. Mick-elson, R. Joseph, M. Vachharajani, B. Schwartz, and Y. Sun, “Reliability Modeling and Management of Nanophotonic On-Chip Networks,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 20, no. 1, pp. 98 -111, Jan. 2012.
  9. D. Datta, and P. Pande, “BER-based power budget evaluation for optical interconnect topologies in NoCs,” in Circuits and Systems (ISCAS), 2012 IEEE International Symposium on, pp. 2429-2432 2012.
  10. L. Bai, H. Gu, Y. Yang, and K. Wang, “A crosstalk aware routing algorithm for Benes ONoC,” IEICE Electronics Express, vol. 9, no. 12, pp. 1069-074, 2012.
  11. S. Koohi and S. Hessabi, “All-Optical Wavelength-Routed Architecture for a Power-Efficient Network on Chip,” Computers, IEEE Transactions on, vol. PP, no. 99, pp. 1-1, 2012.
  12. Z. Chen, G. Huaxi, Y. Yintang, and C. Ke, “Low Latency and Energy Efficient Optical Network-on-Chip Using Wavelength Assignment,” Photonics Technology Letters, IEEE, vol. 24, no. 24, pp. 2296-2299, Dec. 2012.
  13. S. Bartolini and P. Grani, “A Simple On-chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs,” 15th Euromicro Conference on Digital System Design (DSD), pp. 312-318, 2012.
  14. Y. Zheng, P. Lisherness, M. Gao, J. Bovington, S. Yang, and K.-T. Cheng, “Power-efficient calibration and reconfiguration for on-chip op-tical communication,” in Design, Automation Test in Europe Conference Exhibition (DATE), 2012, pp. 1501 -1506, March 2012.
  15. L. Bai, H. Gu, Y. Yang, and K. Wang, “A Cluster-based Reconfigurable Optical Network on Chip De-sign,” Photonics and Optoelectronics (SOPO), 2012 Symposium on, pp. 1-4, 2012.
  16. A. Benner, “Optical interconnect opportunities in supercomputers and high end computing,” in Optical Fiber Communication Conference and Exposition (OFC/NFOEC), 2012 and the National Fiber Optic Engineers Conference, 2012, pp. 1-60.
  17. D. Cai and A. Neyer, “Thermal Stability of Optical Coupling Solutions in Silicone-Based Optical Interconnects,” Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol. 3, no. 2, pp. 213-220, Feb. 2012.
  18. R. Ho, P. Amberg, E. Chang, P. Koka, J. Lexau, G. Li, F. Liu, H. Schwetman, I. Shubin, H. Thacker, X. Zheng, J. Cunningham, and A. Krishnamoorthy, “Silicon photonic interconnects for large-scale computer systems,” Micro, IEEE, vol. PP, p. 99, 2012.
  19. J. Chan and K. Bergman, “Photonic Interconnection Network Architectures Using Wavelength-Selective Spatial Routing for Chip-Scale Communications,” Optical Communications and Networking, IEEE/OSA Journal of, vol. 4, no. 3, pp. 189-201, Mar 2012.
  20. D. Ding, B. Yu, and D. Z. Pan, “GLOW: A Global Router for Low-Power Thermal-Reliable Interconnect Synthesis using Photonic Wavelength Multiplexing,” in Asia and South Pacific Design Automation Conference (ASPDAC), 2012.
  21. Q. Feng, X. Sang, and W. Dou., “Demonstration of a 5 Gb/s x 24 inter-chip optical interconnect system,” Microwave and Optical Technology Letters, vol. 54, pp. 1176-1179, 2012.
  22. T. Hu, P. Yu, C. Qiu, W. Wang, H. Qiu, A. Shen, X. Jiang, M. Yang, and J. Yang, “Non-blocking wavelength-routed 44 silicon optical router for on-chip photonics networks,” in Optical Interconnects Conference, 2012 IEEE, pp. 104-105, 2012.
  23. A. Aboketaf, L. Cao, D. Adams, A. W. Elshaari, S. F. Preble, M. T. Crowley, L. F. Lester, P. Ampadu, “Hybrid OTDM and WDM for multicore optical communication,” International Green Computing Conference (IGCC), 2012.
  24. P. K. Kaliraj, P. Sieber, A. Ganguly, I. Datta, and D. Datta, “Performance evaluation of reliability aware photonic Network-on-Chip architectures,” in Green Computing Conference (IGCC), 2012 International, 2012.
  25. H. A. Khouzani, S. Koohi, and S. Hessabi, “Fully contention-free optical NoC based on wavelength routing,” CSI International Symposium on Computer Architecture and Digital Systems (CADS), pp. 81-86, 2012.
  26. S. Koohi, Y. Yin, S. Hessabi, and S. J. B. Yoo, “Energy efficient all-optical arbitration in optical Network-on-Chip,” in Optical Fiber Communication Conference and Exposition (OFC/NFOEC), 2012 and the National Fiber Optic Engineers Conference, pp. 1-3, March 2012.
  27. Parini, L. Ramini, F. Lanzoni, G. Bellanca, and D. Bertozzi, “Bottom-Up Abstract Modelling of Optical Networks-on-Chip: From Physical to Architectural Layer,” International Journal of Optics, 2012.
  28. Qouneh, Z. Li, M. Joshi, W. Zhang, X. Fu, and T. Li, “Aurora: A thermally resilient photonic network-on-chip architecture,” in Computer Design (ICCD), 2012 IEEE 30th International Conference on, pp. 379-386, 2012.
  29. X. Tan, M. Yang, L. Zhang, Y. Jiang, and Y. Yang, “A Generic Optical Router Design for Photonic Network-on-Chips,” Lightwave Technology, Journal of, vol. 30, no. 3, pp. 368 -376, Feb.1, 2012.
  30. A. Taubenblatt, “Optical Interconnect for High-Performance Computing,” Lightwave Technology, Journal of, vol. 30, no. 4, pp. 448-457, Feb 2012.
  31. K. Wang, A. Nirmalathas, C. Lim, E. Skafidas, and K. Alameh, “Performance of reconfigurable free-space card-to-card optical interconnects under atmospheric turbulence,” 2012 Photonics Global Conference (PGC), pp. 1-5, 2012.
  32. Z. Wang, H. Gu, Y. Yang, and Y. Li, “Ring based Optical Network-on-Chip,” Optics Communications, vol. 285, no. 6, pp. 1010 - 1016, 2012.
  33. Yang, R. Ji, L. Zhang, J. Ding, Y. Tian, P. Zhou, Y. Lu, and W. Zhu, “Optical routers with ultra-low power consumption for photonic networks-on-chip,” in Lasers and Electro-Optics (CLEO), 2012 Conference on, pp. 1-2, 2012.
  34. A. Bianco, D. Cuda, M. Garrich, G. G. Castillo, R. Gaudino, and P. Giaccone, “Optical interconnection networks based on microring resonators,” Optical Communications and Networking, IEEE/OSA Journal of, vol. 4, no. 7, pp. 546-556, July 2012.
  35. W. Fu and T. Chen, “RCBus Row-Column Bus Topology for Optical Network-on-Chip,” ELEKTRONIKA IR ELEKTROTECHNIKA, vol. 18, 2012.
  36. L. Ramini and D. Bertozzi, “The Design Predictability Concern in Optical Network-on-Chip Design,” in Asia Communications and Photonics Conference, OSA Technical Digest (online) (Optical Society of America, 2012), 2012.
  37. L. Zhang, E. E. Regentova, and X. Tan, “Packet switching optical network-on-chip architectures,” Computers & Electrical Engineering, April 2012.
  38. R. Morris, A. Kodi, A. Louri, “Reconfiguration of 3D Photonic On-chip Interconnects for Maximizing Performance and Improving Fault Tolerance,” IEEE/ACM International Symposium on Microarchitecture, Vancouver, BC, Canada, Dec 1-5, 2012.
  39. R. Morris, A. Kodi, A. Louri, “3D-NoC: 3D Reconfigurable Nanophotonic Interconnects for Multicores,” IEEE International Conference on Computer Design, Montreal, Quebec, Canada, September 30- October 2, 2012.

2011

  1. Yaoyao Ye, Jiang Xu*, Xiaowen Wu, Wei Zhang, Xuan Wang, Nikdast, M. Zhehui Wang, Weichen Liu, , “Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip,” IEEE Computer Society Annual Symposium on VLSI, July 2011. [PDF]
  2. Yiyuan Xie, Jiang Xu*, Jianguo Zhang, “Elimination of cross-talk in silicon-on-insulator waveguide crossings with optimized angle,” Optical Engineering, vol. 50, no. 6, June, 2011.
  3. Vantrease, D. Lipasti, M.H. Binkert, N. , “Atomic Coherence: Leveraging nanophotonics to build race-free cache coherence protocols,” High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on, vol., no., pp.132-143, 12-16 Feb. 2011.
  4. Jin Ouyang, Yuan Xie, , “Enabling quality-of-service in nanophotonic network-on-chip,” Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, vol., no., pp.351-356, 25-28 Jan. 2011.
  5. Le Beux, S. Trajkovic, J. O’Connor, I. Nicolescu, G. Bois, G. Paulin, P. , “Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, vol., no., pp.1-6, 14-18 March 2011.
  6. Le Beux, S. Trajkovic, J. O’Connor, I. Nicolescu, G. , “Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC),” VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on, vol., no., pp.242-247, 3-5 Oct. 2011.
  7. Lei Zhang, Regentova, E.E. Xianfang Tan, , “A 2D-Torus Based Packet Switching Optical Network-on-Chip Architecture,” Photonics and Optoelectronics (SOPO), 2011 Symposium on, vol., no., pp.1-4, 16-18 May 2011.
  8. Xianfang Tan, Mei Yang, Lei Zhang, Yingtao Jiang, Jianyi Yang, , “On a Scalable, Non-Blocking Optical Router for Photonic Networks-on-Chip Designs,” Photonics and Optoelectronics (SOPO), 2011 Symposium on, vol., no., pp.1-4, 16-18 May 2011.
  9. Hyeong Ju Kim, Jung Tack Seo, Tae Hee Han, , “3CEO: Three dimensional Cmesh based electrical-optical router for networks-on-chip,” ICT Convergence (ICTC), 2011 International Conference on, vol., no., pp.114-119, 28-30 Sept. 2011.
  10. Channoufi, M. Lecoy, P. Attia, R. Delacressonniere, B. Garcia, S. , “Toward All Optical Interconnections in Chip Multiprocessor (2),” Reconfigurable Computing and FPGAs (ReConFig), 2011 International Conference on, vol., no., pp.501-504, Nov. 30 2011-Dec. 2 2011.
  11. Koohi, S. Abdollahi, M. Hessabi, S. , “All-optical wavelength-routed NoC based on a novel hierarchical topology,” Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on, vol., no., pp.97-104, 1-4 May 2011.
  12. Koohi, S. Shafaei, A. Hessabi, S. , “An Optical Wavelength Switching Architecture for a High-Performance Low-Power Photonic NoC,” Advanced Information Networking and Applications (WAINA), 2011 IEEE Workshops of International Conference on, vol., no., pp.1-6, 22-25 March 2011.
  13. Koohi, S. Hessabi, S. , “Power efficient nanophotonic on-chip network for future large scale multiprocessor architectures,” Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on, vol., no., pp.114-121, 8-9 June 2011.
  14. Abousamra, A. Melhem, R. Jones, A. , “Two-hop Free-space based optical interconnects for chip multiprocessors,” Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on, vol., no., pp.89-96, 1-4 May 2011.
  15. Xuezhe Zheng, Koka, P. McCracken, M.O. Schwetman, H. Mitchell, J.G. Jin Yao, Ho, R. Raj, K. Krishnamoorthy, A.V. , “Energy-Efficient Error Control for Tightly Coupled Systems Using Silicon Photonic Interconnects,” Optical Communications and Networking, IEEE/OSA Journal of, vol.3, no.8, pp.A21-A31, August 2011.
  16. Chan, J. Hendry, G. Bergman, K. Carloni, L.P. , “Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.30, no.10, pp.1507-1520, Oct. 2011.
  17. Krishnamoorthy, A.V. Goossen, K.W. Jan, W. Xuezhe Zheng, Ho, R. Guoliang Li, Rozier, R. Liu, F. Patil, D. Lexau, J. Schwetman, H. Dazeng Feng, Asghari, M. Pinguet, T. Cunningham, J.E. , “Progress in Low-Power Switched Optical Interconnects,” Selected Topics in Quantum Electronics, IEEE Journal of, vol.17, no.2, pp.357-376, March-April 2011.
  18. Brunina, D. Lai, C.P. Garg, A.S. Bergman, K. , “Building Data Centers With Optically Connected Memory,” Optical Communications and Networking, IEEE/OSA Journal of, vol.3, no.8, pp.A40-A48, August 2011.
  19. Green, W.M.J. Min Yang, Assefa, S. Van Campenhout, J. Lee, B.G. Jahnes, C.V. Doany, F.E. Schow, C.L. Kash, J.A. Vlasov, Y.A. , “Silicon electro-optic 44 non-blocking switch array for on-chip photonic networks,” Optical Fiber Communication Conference and Exposition (OFC/NFOEC), 2011 and the National Fiber Optic Engineers Conference, vol., no., pp.1-3, 6-10 March 2011.
  20. Fiorentino, M. Zhen Peng, Binkert, N. Beausoleil, R.G. , “Devices and architectures for large scale integrated silicon photonics circuits,” Winter Topicals (WTM), 2011 IEEE, vol., no., pp.131-132, 10-12 Jan. 2011.
  21. Hendry, G. Chan, J. Carloni, L.P. Bergman, K. , “VANDAL: A tool for the design specification of nanophotonic networks,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, vol., no., pp.1-6, 14-18 March 2011.
  22. Binkert, N. Fiorentino, M. , “Photonic interconnection networks for multicore architectures,” Optical Fiber Communication Conference and Exposition (OFC/NFOEC), 2011 and the National Fiber Optic Engineers Conference, vol., no., pp.1-3, 6-10 March 2011.
  23. Quanyou Feng, Dongson Ban, Huanzhong Li, Wenhua Dou, , “Optical burst switching for many-core processor-to-memory photonic networks,” Computer Science & Education (ICCSE), 2011 6th International Conference on, vol., no., pp.541-546, 3-5 Aug. 2011.
  24. Zheng Li, Mohamed, M. Xi Chen, Mickelson, A. Li Shang, , “Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performance,” Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE , vol., no., pp.735-740, 5-9 June 2011.
  25. Ciftcioglu, B. Berman, R. Jian Zhang, Darling, Z. Shang Wang, Jianyun Hu, Jing Xue, Garg, A. Jain, M. Savidis, I. Moore, D. Huang, M. Friedman, E.G. Wicks, G. Hui Wu, , “A 3-D Integrated Intrachip Free-Space Optical Interconnect for Many-Core Chips,” Photonics Technology Letters, IEEE, vol.23, no.3, pp.164-166, Feb.1, 2011.
  26. R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Five-port optical router for photonic networks-on-chip,” Opt. Express 19, 2011.
  27. R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, and W. Zhu, “Microring-resonator-based four-port optical router for photonic networks-on-chip,” Opt. Express 19, 18945-18955 (2011).
  28. Somayyeh Koohi, Shaahin Hessabi, “Hierarchical opto-electrical on-chip network for future multiprocessor architectures,” Journal of Systems Architecture, Volume 57, Issue 1, January 2011, Pages 4-23.
  29. Aleksandr Biberman, Kyle Preston, Gilbert Hendry, Nicols Sherwood-Droz, Johnnie Chan, Jacob S. Levy, Michal Lipson, and Keren Bergman, “Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors.” J. Emerg. Technol. Comput. Syst, July 2011.
  30. Raymond G. Beausoleil. “Large-scale integrated photonics for high-performance interconnects.” J. Emerg. Technol. Comput. Syst, July 2011.
  31. Zheng Li, Moustafa Mohamed, Xi Chen, Hongyu Zhou, Alan Mickelson, Li Shang, and Manish Vachharajani. “Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication.” J. Emerg. Technol. Comput. Syst, July 2011.
  32. Mark J. Cianchetti and David H. Albonesi. “A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors.” J. Emerg. Technol. Comput. Syst, July 2011.
  33. Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, and Zhiwen Liu. “F2BFLY: an on-chip free-space optical network with wavelength-switching.” In Proceedings of the international conference on Supercomputing (ICS '11), 2011.
  34. Aleksandr Biberman; Nicolás Sherwood-Droz; Xiaoliang Zhu; Kyle Preston; Gilbert Hendry; Jacob S. Levy; Johnnie Chan; Howard Wang; Michal Lipson; Keren Bergman, “Photonic network-on-chip architecture using 3D integration,“ Proc. Of SPIE, 2011.
  35. Chan, J. Ophir, N. Lai, C.P. Biberman, A. Lira, H.L.R. Lipson, M. Bergman, K. , “Data transmission using wavelength-selective spatial routing for photonic interconnection networks,” Optical Fiber Communication Conference and Exposition (OFC/NFOEC), 2011 and the National Fiber Optic Engineers Conference, vol., no., pp.1-3, 6-10 March 2011.
  36. Aleksandr Biberman, Nicols Sherwood-Droz, Xiaoliang Zhu, Kyle Preston, Gilbert Hendry, Jacob S. Levy, Johnnie Chan, Howard Wang, Michal Lipson, Keren Bergman, “Photonic network-on-chip architecture using 3D integration,” Proc. of SPIE, 2011.
  37. Mohamed, M. Zheng Li, Xi Chen, Mickelson, A. Li Shang, , “Modeling and analysis of micro-ring based silicon photonic interconnect for embedded systems,” Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2011 Proceedings of the 9th International Conference on, vol., no., pp.227-236, 9-14 Oct. 2011.
  38. Ahn, Jung Ho and Beausoleil, Raymond G. and Binkert, Nathan and Davis, Al and Fiorentino, Marco and Jouppi, Norman P. and McLaren, Moray and Monchiero, Matteo and Muralimanohar, Naveen and Schreiber, Robert and Vantrease, Dana. “CMOS Nanophotonics Technology System Implications and a CMP Case Study,” Low Power Networks-on-Chip, Springer US, 2011.
  39. T. Hu, H. Qiu, P. Yu, C. Qiu, W. Wang, X. Jiang, M. Yang, and J. Yang, “Wavelength-selective 4x4 nonblocking silicon optical router for networks-on-chip,” Opt. Lett. 36, 4710-4712 (2011).
  40. Gilbert Hendry, Eric Robinson, Vitaliy Gleyzer, Johnnie Chan, Luca P. Carloni, Nadya Bliss, Keren Bergman, “Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors,” Journal of Parallel and Distributed Computing, Volume 71, Issue 5, May 2011, Pages 641-650.
  41. Alberto Parini, Luca Ramini, Gaetano Bellanca, and Davide Bertozzi, “Abstract modelling of switching elements for optical networks-on-chip with technology platform awareness.” the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip, 2011.
  42. Xuezhe Zheng, Liu, F. Patil, D. Lexau, J. Guoliang Li, Ying Luo, Thacker, H. Shubin, I. Jin Yao, Raj, K. Cunningham, J.E. Ron Ho, Krishnamoorthy, A.V. , “Sub pJ/bit WDM silicon photonic communications for many-core computing systems,” Information Photonics (IP), 2011 ICO International Conference on, vol., no., pp.1-2, 18-20 May 2011.
  43. Beausoleil, R.G. Fiorentino, M. McLaren, M. , “Terabit optical interconnects for exascale data centers,” Photonics Society Summer Topical Meeting Series, 2011 IEEE, vol., no., pp.137-138, 18-20 July 2011.
  44. Cisse Ahmadou Dit ADI, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga, “An Efficient Path Setup for a Hybrid Photonic Network-on-Chip,” International Journal of Networking and Computing, Volume 1, Number 2, pages 244-259, July 2011.
  45. Yu-Hsiang Kao, Chao, H.J. , “BLOCON: A Bufferless Photonic Clos network-on-chip architecture,” Networks on Chip (NoCS), May 2011.
  46. Pasricha, S. Bahirat, S. , “OPAL: A multi-layer hybrid photonic NoC for 3D ICs,” Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, vol., no., pp.345-350, 25-28 Jan. 2011.
  47. Heck, Martijn JR, Chen, Hui-Wen, Fang, Alexander W. Koch, Brian R. Liang, Di, Park, Hyundai, Sysak, Matthew N. Bowers, John E, “Hybrid Silicon Photonics for Optical Interconnects,” IEEE Journal of Selected Topics in Quantum Electronics, Vol. 17, no. 2, pp. 333-346, Mar 2011.
  48. Randy Morris and Avinash Karanth Kodi, “Design of a High-Speed Nanophotonic Architecture for Cache Coherent Multicores,” Optical Fiber Communication Conference and Exposition, 2011.

2010

  1. Yiyuan Xie, Mahdi Nikdast, Jiang Xu*, Wei Zhang, Qi Li, Xiaowen Wu, Yaoyao Ye, Weichen Liu, Xuan Wang, “Crosstalk Noise and Bit Error Rate Analysis for Optical Network-on-Chip,” in Proceedings ofDesign Automation Conference (DAC), 2010. [PDF]
  2. Xiaowen Wu, Yaoyao Ye, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang, Jiang Xu*, “UNION: A Unified Inter/Intra-Chip Optical Network for Chip Multiprocessors,” in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), June 2010. [PDF]
  3. Kwai Hung Mo, Yaoyao Ye, Xiaowen Wu, Wei Zhang, Weichen Liu, Jiang Xu*, “A Hierarchical Hybrid Optical-Electronic Network-on-Chip,” in Proceedings ofIEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2010. [PDF]
  4. Huaxi Gu, Shiqing Wang, Yintang Yang, Jiang Xu, “Design of Butterfly-Fat-Tree Optical Network-on-Chip,” Optical Engineering, vol 49, issue 9, 2010.
  5. Biberman, A. Chan, J. Bergman, K. , “On-chip optical interconnection network performance evaluation using power penalty metrics from silicon photonic modulators,” Interconnect Technology Conference (IITC), 2010 International, vol., no., pp.1-3, 6-9 June 2010.
  6. Hendry, Gilbert, Robinson, Eric, Gleyzer, Vitaliy, Chan, Johnnie, Carloni, Luca, Bliss, Nadya, Bergman, Keren, , “Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing,” High Performance Computing, Networking, Storage and Analysis (SC), 2010 International Conference for, vol., no., pp.1-12, 13-19 Nov. 2010.
  7. Biberman, A. Lee, B. Sherwood Droz, N. Lipson, M. Bergman, K. , “Broadband Operation of Nanophotonic Router for Silicon Photonic Networks-on-Chip,” IEEE Photonics Technology Letters, 2010.
  8. Hendry, G. Chan, J. Kamil, S. Oliker, L. Shalf, J. Carloni, L.P. Bergman, K. , “Silicon Nanophotonic Network-on-Chip Using TDM Arbitration,” High Performance Interconnects (HOTI), 2010 IEEE 18th Annual Symposium on, vol., no., pp.88-95, 18-20 Aug. 2010.
  9. Chan, J. Hendry, G. Biberman, A. Bergman, K. , “Architectural Exploration of Chip-Scale Photonic Interconnection Network Designs Using Physical-Layer Analysis,” Journal of Lightwave Technology, 2010.
  10. Lee, B.G. Biberman, A. Chan, J. Bergman, K. , “High-Performance Modulators and Switches for Silicon Photonic Networks-on-Chip,” IEEE Journal of Selected Topics in Quantum Electronics, 2010.
  11. Chan, J. Hendry, G. Biberman, A. Bergman, K. , “Tools and methodologies for designing energy-efficient photonic networks-on-chip for highperformance chip multiprocessors,” Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, vol., no., pp.3605-3608, May 30 2010-June 2 2010.
  12. J. Chan, G. Hendry, A. Biberman, K. Bergman, and L. P. Carloni. “Phoenixsim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks,” In DATE: Design, Automation, and Test in Europe., 2010.
  13. Ron Ho, Liu, F. Patil, D. Xuezhe Zheng, Guoliang Li, Shubin, I. Alon, E. Lexau, J. Schwetman, H. Cunningham, J. Krishnamoorthy, A.V. , “Optical Interconnect for High-End Computer Systems,” Design & Test of Computers, IEEE, vol.27, no.4, pp.10-19, July-Aug. 2010.
  14. Jing Xue, Alok Garg, Berkehan Ciftcioglu, Shang Wang, Jianyun Hu, Ioannis Savidis, Manish Jain, Michael Huang, Hui Wu, Eby G. Friedman, Gary W. Wicks, Duncan Moore, “An Intra-Chip Free-Space Optical Interconnect,” ISCA, 2010
  15. Lee, Y. Zhang, Y. , “Performance Comparison and Overview of Different Approaches for VLSI Optoelectronic Interconnects,” Journal of Optical Communications and Networking, 2010.
  16. Morris, R. Kodi, A. K. , “Exploring the Design of 64- and 256-core Power Efficient Nanophotonic Interconnect,” IEEE Journal of Selected Topics in Quantum Electronics, 2010.
  17. Pan, Yan, Kim, John, Memik, Gokhan, , “FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar,” 16th IEEE International Symposium on High Performance Computer Architecture (HPCA), 2010.
  18. Stojanovic, V. Joshi, A. Batten, C. Yong-Jin Kwon, Beamer, S. Sun Chen, Asanovic, K. , “CMOS photonic processor-memory networks,” IEEE Photonics Society Winter Topicals Meeting Series (WTM), 2010.
  19. Young, I. A. Mohammed, E. Liao, J. T. S. Kern, A. M. Palermo, S. Block, B. A. Reshotko, M. R. Chang, P. L. D. , “Optical I/O Technology for Tera-Scale Computing,” IEEE Journal of Solid-State Circuits, 2010.
  20. Young, I.A. Mohammed, E.M. Liao, J.T.S. Kern, A.M. Palermo, S. Block, B.A. Reshotko, M.R. Chang, P.L.D. , “Optical technology for energy efficient I/O in high performance computing,” Communications Magazine, IEEE, vol.48, no.10, pp.184-191, October 2010.
  21. Nevin Kirman, Jose F. Martinez, “A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing,” Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems, 2010.
  22. Le Beux, Sebastien, Nicolescu, Gabriela, Bois, Guy, Paulin, Pierre, , “A system-level exploration flow for optica network on chip (ONoC) in 3D MPSoC,” Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, vol., no., pp.3613-3616, May 30 2010-June 2 2010.
  23. Psota, James, Miller, Jason, Kurian, George, Hoffman, Henry, Beckmann, Nathan, Eastep, Jonathan, Agarwal, Anant, , “ATAC: Improving performance and programmability with on-chip optical networks,” Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, vol., no., pp.3325-3328, May 30 2010-June 2 2010.
  24. Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li, , “Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, vol., no., pp.933-936, 8-12 March 2010.
  25. Allam, Atef, O’Connor, Ian, Scandurra, Alberto, , “Optical network-on-chip reconfigurable model for multi-level analysis,” Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, vol., no., pp.3609-3612, May 30 2010-June 2 2010.
  26. Le Beux, S. Trajkovic, J. O’Connor, I. Nicolescu, G. Bois, G. Paulin, P. , “Multi-Optical Network on Chip for Large Scale MPSoC,” Embedded Systems Letters, IEEE, vol.PP, no.99, pp.1-1, 2010.
  27. Allam, Atef, O’Connor, Ian, Heirman, Wim, , “Performance evaluation for passive-type Optical network-on-chip,” Rapid System Prototyping (RSP), 2010 21st IEEE International Symposium on, vol., no., pp.1-7, 8-11 June 2010.
  28. Koohi, S. Hessabi, S. , “Hierarchical on-Chip Routing of Optical Packets in Large Scale MPSoCs,” Parallel, Distributed and Network-Based Processing (PDP), 2010 18th Euromicro International Conference on, vol., no., pp.515-524, 17-19 Feb. 2010.
  29. Morris, R.W. Kodi, A.K. , “Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores,” Networks-on-Chip (NOCS), 2010 Fourth ACM/IEEE International Symposium on, vol., no., pp.207-214, 3-6 May 2010.
  30. Zhang, Xiang, Louri, Ahmed, , “A multilayer nanophotonic interconnection network for on-chip many-core communications,” Design Automation Conference (DAC), 2010 47th ACM/IEEE , vol., no., pp.156-161, 13-18 June 2010.
  31. Lin Liu, Yuanyuan Yang, , “Energy-aware routing in hybrid optical network-on-chip for future Multi-Processor System-on-Chip,” Architectures for Networking and Communications Systems (ANCS), 2010 ACM/IEEE Symposium on, vol., no., pp.1-9, 25-26 Oct. 2010.
  32. Bahirat, Shirish, Pasricha, Sudeep, , “UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications,” 11th International Symposium on Quality Electronic Design (ISQED), 2010.
  33. Zheng Li, Mohamed, M. Hongyu Zhou, Li Shang, Mickelson, A. Filipovic, D. Vachharajani, M. Wounjhang Park, Yihe Sun, , “Global On-Chip Coordination at Light Speed,” Design & Test of Computers, IEEE, vol.27, no.4, pp.54-67, July-Aug. 2010.
  34. Jung Ho Ahn, Raymond G. Beausoleil, Nathan Binkert, Al Davis, Marco Fiorentino, Norman P. Jouppi, Moray McLaren, Matteo Monchiero, Naveen Muralimanohar and Robert Schreiber, et al., “CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study,” Low power networks-on-chip, Springer US.

2009

  1. Huaxi Gu, Jiang Xu*, Wei Zhang, “A Low-power Fat Tree-based Optical Network-on-Chip for Multiprocessor System-on-Chip,” Design, Automation and Test in Europe Conference and Exhibition (DATE), 2009. [PDF]
  2. Yaoyao Ye, Lian Duan, Jiang Xu*, Jin Ouyang, Kwai Hung Mo, Yuan Xie, “3D Optical NoC for MPSoC,” IEEE International 3D System Integration Conference (3DIC), 2009. [PDF]
  3. Huaxi Gu, Kwai Hung Mo, Jiang Xu*, Wei Zhang, “A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2009. [PDF]
  4. Huaxi Gu, Jiang Xu*, “Design of 3D Optical Network on Chip,” in Proceedings of International Symposium on Photonics and Optoelectronics (SOPO), 2009. [PDF]
  5. Allam, A. O’Connor, I. Drouard, E. Mieyeville, F. Scandurra, A. , “Optical NoC design-parameters exploration and analysis,” 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2009.
  6. Van Thourhout, D. O’Connor, I. Scandurra, A. Liu, L. Bogaerts, W. Selvaraja, S. Roelkens, G. , “Nanophotonic devices for optical networks-on-chip,” Conference on Lasers and Electro-Optics and Conference on Quantum electronics and Laser Science Conference (CLEO/QELS), 2009.
  7. Lee, B.G. Biberman, A. Bergman, K. Sherwood-Droz, N. Lipson, M. , “Multi-wavelength message routing in a non-blocking four-port bidirectional switch fabric for silicon photonic networks-on-chip,” Conference on Optical Fiber Communication (OFC), 2009.
  8. Bergman, K. , “Nanophotonic interconnection networks in multicore embedded computing,” IEEE/LEOS Winter Topicals Meeting Series, 2009.
  9. Lee, B.G. Biberman, A. Sherwood-Droz, N. Poitras, C.B. Lipson, M. Bergman, K. , “High-Speed 2 x 2 Switch for Multiwavelength Silicon-Photonic Networks-On-Chip,” Journal of Lightwave Technology, 2009.
  10. Petracca, M. Lee, B.G. Bergman, K. Carloni, L.P. , “Photonic NoCs: System-Level Design Exploration,” IEEE Micro, 2009.
  11. Artundo, I. Heirman, W. Loperena, M. Debaes, C. Van Campenhout, J. Thienpont, H. , “Low-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects,” 17th IEEE Symposium on High Performance Interconnects (HOTI), 2009.
  12. Batten, C. Joshi, A. Orcutt, J. Holzwarth, C. Popovic, M. Hoyt, J. Kartner, F. Ram, R. Stojanovic, V. Asanovic, K. , “Building Manycore Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics,” IEEE Micro, 2009.
  13. Carloni, L.P. Pande, P. Yuan Xie, , “Networks-on-chip in emerging interconnect paradigms: Advantages and challenges,” 3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCS), 2009.
  14. D. Ding and D. Z. Pan, “OIL: A nano-photonics optical interconnect library for a new photonic networks-on-chip architecture,” In Intl. Wkshp. on System-Level Interconnect Prediction, 2009.
  15. Debaes, C. Artundo, I. Heirman, W. Loperena, M. Van Campenhout, J. Thienpont, H. , “Architectural study of reconfigurable photonic Networks-on-Chip for multi-core processors,” LEOS Annual Meeting Conference Proceedings, 2009.
  16. Duo Ding, Yilin Zhang, Haiyu Huang, Chen, R.T. Pan, D.Z. , “O-Router: An optical routing framework for low power on-chip silicon nano-photonic integration,” 46th ACM/IEEE Design Automation Conference (DAC), 2009.
  17. El-Hang Lee, , “VLSI Photonics: Science and engineering of high-density photonic circuit integration in micro/nano-scale,” 11th International Conference on Transparent Optical Networks (ICTON), 2009.
  18. J. Ahn, M. Fiorentino1, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease and Q. Xu, “Devices and architectures for photonic chip-scale integration,” Journal of Applied Physics A: Materials Science & Processing, 2009.
  19. Jason Miller, James Psota, George Kurian, Nathan Beckmann, Jonathan Eastep, Jifeng Liu, Mark Beals, Jurgen Michel, Lionel Kimerling, and Anant Agarwal, “ATAC: A Manycore Processor with On-Chip Optical Network,” MIT CSAIL Technical Report, 2009.
  20. Huimin Zhang, Yaojun Qiao, Yuefeng Ji, , “A novel asymmetric optical interconnection network architecture for network-on-chip,” IEEE International Conference on Network Infrastructure and Digital Content (IC-NIDC), 2009.
  21. Yu Gao, Yaohui Jin, Zhijuan Chang, Weisheng Hu, , “Ultra-low latency reconfigurable Photonic Network on Chip architecture based on application pattern,” Conference on Optical Fiber Communication (OFC), 2009.
  22. Jianxiong Tang, Yaohui Jin, Zhijuan Chang, , “Deflection routing in multi-channel photonic network on chip architecture,” Asia Communications and Photonics conference and Exhibition (ACP), 2009.
  23. Joshi, A. Batten, C. Yong-Jin Kwon, Beamer, S. Shamim, I. Asanovic, K. Stojanovic, V. , “Silicon-photonic clos networks for global on-chip communication,” 3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCS), 2009.
  24. Kazmierczak, A. Bogaerts, W. Drouard, E. Dortu, F. Rojo-Romeo, P. Gaffiot, F. Van Thourhout, D. Giannone, D. , “Highly Integrated Optical 4 x 4 Crossbar in Silicon-on-Insulator Technology,” Journal of Lightwave Technology, 2009.
  25. Kodi, A. K. Morris, R. Louri, A. Xiang Zhang, , “On-Chip photonic interconnects for scalable multi-core architectures,” 3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCS), 2009.
  26. Koohi, S. Hessabi, S. , “Contention-free on-chip routing of optical packets,” 3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCS), 2009.
  27. Krishnamoorthy, A.V. Ho, R. Xuezhe Zheng, Schwetman, H. Lexau, J. Koka, P. Guoliang Li, Shubin, I. Cunningham, J.E. , “The integration of silicon photonics and VLSI electronics for computing systems,” International Conference on Photonics in Switching (PS), 2009.
  28. Lira, H.L.R. Manipatruni, S. Lipson, M. , “Broadband hitless silicon electro-optic switch for optical networkson-chip,” 6th IEEE International Conference on Group IV Photonics (GFP), 2009.
  29. M.J. Cianchetti, J.C. Kerekes, and D.H. Albonesi, “Phastlane: A Rapid Transit Optical Routing Network,” 36th International Symposium on Computer Architecture, June 2009.
  30. Norman P. Jouppi, “System implications of integrated photonics,” Proceeding of the 13th international symposium on Low power electronics and design, 2009.
  31. Ohashi, K. Nishi, K. Shimizu, T. Nakada, M. Fujikata, J. Ushida, J. Torii, S. Nose, K. Mizuno, M. Yukawa, H. Kinoshita, M. Suzuki, N. Gomyo, A. Ishi, T. Okamoto, D. Furue, K. Ueno, T. Tsuchizawa, T. Watanabe, T. Yamada, K. Itabashi, S.-i. Akedo, J. , “On-Chip Optical Interconnect,” Proceedings of the IEEE, 2009.
  32. Poon, A.W. Xianshu Luo, Fang Xu, Hui Chen, , “Cascaded Microresonator-Based Matrix Switch for Silicon On-Chip Optical Interconnection,” Proceedings of the IEEE, 2009.
  33. Rajeev K. Dokania, Alyssa B. Apsel, “Analysis of Challenges for On-Chip Optical Interconnects,” Proceedings of the 19th ACM Great Lakes symposium on VLSI, 2009.
  34. Stojanovic, V. Joshi, A. Batten, C. Yong-jin Kwon, Asanovic, K. , “Manycore processor networks with monolithic integrated CMOS photonics,” Conference on Lasers and Electro-Optics and Conference on Quantum electronics and Laser Science Conference (CLEO/QELS), 2009.
  35. Tsybeskov, L. Lockwood, D.J. Ichikawa, M. , “Silicon Photonics: CMOS Going Optical,” Proceedings of the IEEE, 2009.
  36. Wada, K. , “Challenges of Si photonics for on-chip integration,” 35th European Conference on Optical Communication (ECOC), 2009.
  37. Xianshu Luo, Shaoqi Feng, Poon, A.W. , “Dual-microring resonator-coupled cross-connect switch element for on-chip optical interconnection,” 14th OptoElectronics and Communications Conference (OECC), 2009.
  38. Yan Pan, Prabhat Kumar, John Kim, Gokhan Memik, Yu Zhang, Alok Choudhary, “Firefly: Illuminating future network-on-chip with nanophotonics,” In Proc. of the Int’l Symposium on Computer Architecture (ISCA), 2009.
  39. Zheng Li, Fay, D. Mickelson, A. Li Shang, Vachharajani, M. Filipovic, D. Wounjhang Park, Yihe Sun, , “Spectrum: A hybrid nanophotonicelectric on-chip network,” 46th ACM/IEEE Design Automation Conference (DAC), 2009.

2008

  1. Huaxi Gu, Jiang Xu*, Zheng Wang, “ODOR: a Microresonator-based High-performance Low-cost Router for Optical Networks-on-Chip,” in Proceedings of International Conference on Hardware-Software Codesign and System Synthesis (CODES), 2008. [PDF]
  2. Huaxi Gu, Jiang Xu*, Zheng Wang, “A Novel Optical Mesh Network-on-Chip for Gigascale Systems-on-Chip,” in Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2008. [PDF]
  3. Huaxi Gu, Jiang Xu*, Zheng Wang, “Design of Sparse Mesh for Optical Network on Chip,” in Proceedings of IEEE Asia Pacific Optical Communications (APOC), 2008.
  4. A. Jain, S. Kamil, M. Mohiyuddin, J. Shalf, and J. Kubiatowicz, “Performance and Energy Comparison of Electrical and Hybrid Photonic Networks for CMPs,” The Applied Power Electronics Conference and Exposition, 2008.
  5. Alberto Scandurra, Ian OConnor, “Scalable CMOS-compatible photonic routing topologies for versatile networks on chip,” NoCArc, 2008.
  6. I. O’Connor et al., “Reduction methods for adapting optical network on chip topologies to specific routing applications,” Proc. DCIS, 2008.
  7. Andrew W. Poon, Fang Xu, and Xianshu Luo, “Cascaded active silicon microresonator array cross-connect circuits for WDM networks-on-chip,” Silicon Photonics III Conference, Photonics West 2008.
  8. Batten, C. Joshi, A. Orcutt, J. Khilo, A. Moss, B. Holzwarth, C. Popovic, M. Hanqing Li, Smith, H. Hoyt, J. Kartner, F. Ram, R. Stojanovic, V. Asanovic, K. , “Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics,” 16th IEEE Symposium on High Performance Interconnects (HOTI), 2008.
  9. Beausoleil, R.G. Ahn, J. Binkert, N. Davis, A. Fattal, D. Fiorentino, M. Jouppi, N.P. McLaren, M. Santori, C.M. Schreiber, R.S. Spillane, S.M. Vantrease, D. Xu, Q. , “A Nanophotonic Interconnect for High-Performance Many-Core Computation,” 16th IEEE Symposium on High Performance Interconnects (HOTI), 2008.
  10. Beausoleil, R.G. Kuekes, P.J. Snider, G.S. Shih-Yuan Wang, Williams, R.S. , “Nanoelectronic and Nanophotonic Interconnect,” Proceedings of the IEEE, 2008.
  11. Biberman, A. Lee, B.G. Po Dong, Lipson, M. Bergman, K. , “250 Gb/s multi-wavelength operation of microring resonator-based broadband comb switch for silicon photonic networks-on-chip,” 34th European Conference on Optical Communication (ECOC), 2008.
  12. Lee, B.G. Biberman, A. Po Dong, Lipson, M. Bergman, K. , “All-Optical Comb Switch for Multiwavelength Message Routing in Silicon Photonic Networks,” IEEE Photonics Technology Letters, 2008.
  13. Keren Bergman and Luca Carloni, “Power efficient photonic networks on-chip,” Proc. SPIE 6898, 2008.
  14. Biberman, A. Sherwood-Droz, N. Lee, B.G. Lipson, M. Bergman, K. , “Thermally active 44 non-blocking switch for networks-on-chip,” 21st IEEE Annual Meeting of the Lasers and Electro-Optics Society (LEOS), 2008.
  15. Nicols Sherwood-Droz, Howard Wang, Long Chen, Benjamin G. Lee, Aleksandr Biberman, Keren Bergman, and Michal Lipson, “Optical 4x4 hitless slicon router for optical networks-on-chip (NoC),” Opt. Express 16, 2008.
  16. Lee, B.G. Biberman, A. Sherwood-Droz, N. Poitras, C.B. Lipson, M. Bergman, K. , “High-Speed 22 switch for multi-wavelength message routing in on-chip silicon photonic networks,” 34th European Conference on Optical Communication (ECOC), 2008.
  17. Chan, J. Biberman, A. Lee, B.G. Bergman, K. , “Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications,” 21st IEEE Annual Meeting of the Lasers and Electro-Optics Society (LEOS), 2008.
  18. Lai, C.P. Wang, H. Bergman, K. , “Cross-Layer Communication With an Optical Packet Switched Network via a Message Injection Control Interface,” IEEE Photonics Technology Letters, 2008.
  19. Petracca, M. Bergman, K. Carloni, L.P. , “Photonic networks-on-chip: Opportunities and challenges,” IEEE International Symposium on Circuits and Systems (ISCAS), 2008.
  20. Petracca, M. Lee, B.G. Bergman, K. Carloni, L.P. , “Design Exploration of Optical Interconnection Networks for Chip Multiprocessors,” 16th IEEE Symposium on High Performance Interconnects (HOTI), 2008.
  21. Shacham, A. Bergman, K. Carloni, L.P. , “Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors,” IEEE Transactions on Computers, 2008.
  22. Howard Wang, Petracca, M. Biberman, A. Lee, B.G. Carloni, L.P. Bergman, K. , “Nanophotonic Optical Interconnection Network Architecture for On-Chip and Off-Chip Communications,” Conference on Optical Fiber communication/National Fiber Optic Engineers Conference (OFC/NFOEC), 2008.
  23. Hadke, A. Benavides, T. Yoo, S.J.B. Amirtharajah, R. Akella, V. , “OCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects,” 16th IEEE Symposium on High Performance Interconnects (HOTI), 2008.
  24. J. Fujikata, K. Nishi, A. Gomyo, et al, “LSI On-Chip Optical Interconnection with Si Nano-Photonics,” IEICE Transactions on Electronics, 2008.
  25. Krishnamoorthy, A.V. Lexau, J. Xuezhe Zheng, Cunningham, J.E. Ho, R. Torudbakken, O. , “Optical Interconnects for Present and Future High-Performance Computing Systems,” 16th IEEE Symposium on High Performance Interconnects (HOTI), 2008.
  26. Orcutt, J.S. Khilo, A. Popovic, M.A. Holzwarth, C.W. Moss, B. Hanqing Li, Dahlem, M.S. Bonifield, T.D. Kartner, F.X. Ippen, E.P. Hoyt, J.L. Ram, R.J. Stojanovic, V. , “Demonstration of an electronic photonic integrated circuit in a commercial scaled bulk CMOS process,” Lasers and Electro-Optics and Conference on Quantum Electronics and Laser Science (CLEO/QELS), 2008.
  27. Pasricha, S. Dutt, N. , “ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip,” Asia and South Pacific Design Automation Conference (ASPDAC), 2008.
  28. Tan, M. Rosenberg, P. Jong Souk Yeo, McLaren, M. Mathai, S. Morris, T. Straznicky, J. Jouppi, N.P. Huei Pei Kuo, Shih-Yuan Wang, Lerner, S. Kornilovich, P. Meyer, N. Bicknell, R. Otis, C. Seals, L. , “A High-Speed Optical Multi-Drop Bus for Computer Interconnections,” 16th IEEE Symposium on High Performance Interconnects (HOTI), 2008.
  29. Vantrease, D. Schreiber, R. Monchiero, M. McLaren, M. Jouppi, N.P. Fiorentino, M. Davis, A. Binkert, N. Beausoleil, R.G. Ahn, J.H. , “Corona: System Implications of Emerging Nanophotonic Technology,” 35th International Symposium on Computer Architecture (ISCA), 2008.
  30. Yurii Vlasov, William M. J. Green and Fengnian Xia, “High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks,” Nature Photonics 2, 2008.

2007

  1. O’Connor, I. Tissafi-Drissi, F. Gaffiot, F. Dambre, J. De Wilde, M. Van Campenhout, J. Van Thourhout, D. Stroobandt, D. , “Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007.
  2. Briere, M. Girodias, B. Bouchebaba, Y. Nicolescu, G. Mieyeville, F. Gaffiot, F. O’Connor, I. , “System Level Assessment of an Optical NoC in an MPSoC Platform,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2007.
  3. Shacham, A. Bergman, K. , “Building Ultralow-Latency Interconnection Networks Using Photonic Integration,” IEEE Micro, 2007.
  4. Shacham, A. Bergman, K. Carloni, L.P. , “On the Design of a Photonic Network-on-Chip,” First International Symposium on Networks-on-Chip (NoCS), 2007.
  5. Shacham, A. Bergman, K. Carloni, L.P. , “The Case for Low-Power Photonic Networks on Chip,” 44th ACM/IEEE Design Automation Conference (DAC), 2007.
  6. Shacham, A. Lee, B.G. Biberman, A. Bergman, K. Carloni, L.P. , “Photonic NoC for DMA Communications in Chip Multiprocessors,” 15th Annual IEEE Symposium on High-Performance Interconnects (HOTI), 2007.
  7. Benjamin A. Small, Benjamin G. Lee, Keren Bergman, Qianfan Xu, and Michal Lipson, “Multiple-wavelength integrated photonic networks based on microring resonator devices,” J. Opt. Netw. 6, 2007.
  8. Biberman, A. Po Dong, Lee, B.G. Foster, J.D. Lipson, M. Bergman, K. , “Silicon Microring Resonator-Based Broadband Comb Switch for Wavelength-Parallel Message Routing,” The 20th IEEE Annual Meeting of the Lasers and Electro-Optics Society (LEOS), 2007.
  9. Gunn, C. , “Fully Integrated VLSI CMOS and Photonics,” 2007 IEEE Symposium on CMOS Photonics, VLSI Technology, 2007.
  10. Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas A. Nelson, David H. Albonesi, Philippe M. Fauchet, and Eby G. Friedman, “On-Chip Optical Interconnect for Reduced Delay Uncertainty,” Proceedings of the 2nd international conference on Nano-Networks, 2007.
  11. Kirman, N. Kirman, M. Dokania, R.K. Martinez, J.F. Apsel, A.B. Watkins, M.A. Albonesi, D.H. , “On-Chip Optical Technology in Future Bus-Based Multicore Designs,” IEEE Micro, 2007.
  12. Roychowdhury, J. , “Micro-Photonic Interconnects: Characteristics, Possibilities and Limitations,” 44th ACM/IEEE Design Automation Conference (DAC), 2007.

2006

  1. I. O’Connor, F. Tissafi-Drissi, D. Navarro, F. Mieyeville, F. Gaffiot, J. Dambre, M. De Wilde, D. Stroobandt, D. Van Thourhout, “Optical interconnect for on-chip data communication,” Future Interconnects and Networks on Chip : special workshop co-located with DATA, 2006.
  2. I. O’Connor, F. Tissafi-Drissi, D. Navarro, F. Mieyeville, F. Gaffiot, J. Dambre, M. de Wilde, D. Stroobandt, M. Briere, , “Integrated optical interconnect for on-chip data transport,” IEEE North-East Workshop on Circuits and Systems, 2006.
  3. W. Eirmana, J. Dambrea, I. O’Connorb , J. Van Campenhout, “Reconfigurable Optical Networks for On-Chip Multiprocessors,” Photonic Network Communications, pp. , 2016, ISSN 1387-974X.
  4. Benjamin G Lee, Benjamin A Small, Keren Bergman, Qianfan Xu, Michal Lipson, “Transmission of high-data-rate optical signals through a micrometer-scale silicon ring resonator,” Optics letters, 2006.
  5. C. Gunn, “CMOS Photonics for High-Speed Interconnects,” IEEE Micro, 2006.
  6. C. Gunn “CMOS Photonics technology enabling optical interconnects” Photonics West, 2006.
  7. Fengnian Xia, Lidija Sekaric and Yurii Vlaso, “Ultracompact optical buffers on a silicon chip,” Nature Photonics 1, 2006.
  8. Guoqing Chen, Hui Chen, Haurylau, M. Nelson, N.A. Albonesi, D.H. Fauchet, P.M. Friedman, E.G. , “On-Chip Copper-Based vs. Optical Interconnects: Delay Uncertainty, Latency, Power, and Bandwidth Density Comparative Predictions,” Interconnect Technology Conference, 2006.
  9. Haurylau, M. Chen, G. Chen, H. Zhang, J. Nelson, N. A. Albonesi, D. H. Friedman, E. G. Fauchet, P. M. , “On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions,” IEEE Journal of Selected Topics in Quantum Electronics, 2006.
  10. H. Chen and A. W. Poon, “Design of Silicon MMI Crossing Laterally Coupled Microring Resonators,” In Conference on Lasers and Electro-Optics/Quantum Electronics and Laser Science Conference and Photonic Applications Systems Technologies, Optical Society of America, 2006.
  11. Kirman, N. Kirman, M. Dokania, R.K. Martinez, J.F. Apsel, A.B. Watkins, M.A. Albonesi, D.H. , “Leveraging Optical Technology in Future Bus-based Chip Multiprocessors,” 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2006.
  12. Scandurra, A. Lenzi, M. Guerra, R. Delia Corte, F.G. Nigro, M.A. , “Optical Interconnects for Network on Chip,” 1st International Conference on Nano-Networks and Workshops, 2006.

2005

  1. Briere, M. Drouard, E. Mieyeville, F. Navarro, D. O’Connor, I. Gaffiot, F. , “Heterogeneous modelling of an optical network-on-chip with SystemC,” The 16th IEEE International Workshop on Rapid System Prototyping (RSP), 2005.
  2. I. O’Connor et al., “Towards reconfigurable optical networks on chip,” In Reconfigurable Communication-centric Systems-on-Chip workshop, 2005.
  3. Gunn, G. , “Photonics integration for optical interconnects,” The 18th Annual Meeting of the IEEE Lasers and Electro-Optics Society (LEOS), 2005.
  4. Guoqing Chen, Hui Chen, Haurylau, M. Nelson, N. Albonesi, D. Fauchet, P.M. Friedman, E.G. , “Electrical and optical on-chip interconnects in scaled microprocessors,” IEEE International Symposium on Circuits and Systems (ISCAS), 2005.
  5. Guoqing Chen, Hui Chen, Mikhail Haur ylau, Nicholas Nelson Philippe M. Fauchet, and Eby G. Friedman, “Predictions of CMOS compatible on-chip optical interconnect,” Proceedings of the international workshop on System level interconnect prediction, 2005.
  6. Nicholas Nelson, Gregory Briggs, Mikhail Haurylau, Guoqing Chen, Hui Chen, David H. Albonesi, Eby G. Friedman, “Alleviating Thermal Constraints while Maintaining Performance Via Silicon-Based On-Chip Optical Interconnects,” In Proceedings of Workshop on Unique Chips and Systems, 2005.
  7. Haurylau, M. Hui Chen, Jidong Zhang, Guoqing Chen, Nelson, N.A. Albonesi, D.H. Friedman, E.G. Fauchet, P.M. , “On-chip optical interconnect roadmap: challenges and critical directions,” 2nd IEEE International Conference on Group IV Photonics, 2005.
  8. Wang, Z. Fan, Z. Xia, J. Chen, S. Yu, J. , “Rearrangeable nonblocking thermo-optic 44 switching matrix in silicon-on-insulator,” IEE Proceedings Optoelectronics, 2005.

2004 and earlier

  1. I. O’Connor et al., “On-Chip Optical Interconnect for Low-Power,” In E. Macii(Ed), Ultra-Low Power Electronics and Design, Kulwer, Dordrecht, 2004.
  2. I. O’Connor, “Optical Solutions for System-Level Interconnect,” Proceedings of the international workshop on System level interconnect prediction, 2004.
  3. I. O’Connor, F. Gaffiot, “Advanced Research in on-Chip Optical Interconnects,” Lower Power Electronics and Design, 2004.
  4. Piguet, C. Gautier, J. Heer, C. O’Connor, I. Schlichtmann, U. , “Extremely low-power logic,” Design, Automation and Test in Europe Conference and Exhibition, 2004.
  5. Baets, R. Bogaerts, W. Dumon, P. Roelkens, G. Christiaens, I. De Mesel, K. Taillaert, D. Luyssaert, B. Van Campenhout, J. Bienstman, P. Van Thourhout, D. Wiaux, V. Wouters, J. Beckx, S. , “Integration of photonic functions in and with silicon,” Proceeding of the 34th European Solid-State Device Research conference (ESSDERC), 2004.
  6. Graham T. Reed, “The optical age of silicon,” Nature, 2004.
  7. Dawei Huang, Sze, T. Landin, A. Lytel, R. Davidson, H.L. , “Optical interconnects: out of the box forever?,” IEEE Journal of Selected Topics in Quantum Electronics, 2003.
  8. Chung-Seok Seo, Chatterjee, A. , “A CAD tool for system-on-chip placement and routing with free-space optical interconnect,” IEEE International Conference on Computer Design (ICCD), 2002.
  9. Kapur, P. Saraswat, K.C. , “Comparisons between electrical and optical interconnects for on-chip signaling,” Proceedings of the IEEE Interconnect Technology Conference, 2002.
  10. Bontoux, P. and O’Connor, I. and Gaffiot, F. and Letartre, X. and Jacquemod, G., “Behavioral Modeling and Simulation of Optical Integrated Devices,” Analog Integrated Circuits and Signal Processing, 2001.
  11. Little, B.E. Chu, S.T. Pan, W. Kokubun, Y. , “Microring resonator arrays for VLSI photonics,” IEEE Photonics Technology Letters, 2000.
  12. Lytel, R. Davidson, H.L. Nettleton, N. Sze, T. , “Optical interconnections within modern high-performance computing systems,” Proceedings of the IEEE, 2000.
  13. Miller, D.A.B. , “Rationale and challenges for optical interconnects to electronic chips,” Proceedings of the IEEE, 2000.
  14. Little, B.E. Haus, H.A. Foresi, J.S. Kimerling, L.C. Ippen, E.P. Ripin, D.J. , “Wavelength switching and routing using absorption and resonance,” IEEE Photonics Technology Letters, 1998.
  15. Soref, R.A. Little, B.E. , “Proposed N-wavelength M-fiber WDM crossconnect switch using active microring resonators,” IEEE Photonics Technology Letters, 1998.
  16. Spanke, R. , “Architectures for guided-wave optical space switching systems,” IEEE Communications Magazine, 1987.
  17. J. W. Goodman, F. J. Leonberger, S. C. Kung, and R. A. Athale, “Optical Interconnections for VLSI Systems,” Proc. IEEE, 1984.